summaryrefslogtreecommitdiff
path: root/src/northbridge
diff options
context:
space:
mode:
authorStefan Reinauer <stepan@coresystems.de>2010-04-15 23:01:59 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-15 23:01:59 +0000
commite46c1c85c90b6d263f951ab745a9fadd93041111 (patch)
tree4ffefdc0767139b66c48732d44b8a3222eb6b09f /src/northbridge
parentc24d383c15f6d31cd1dd5fb8e090db0561421599 (diff)
downloadcoreboot-e46c1c85c90b6d263f951ab745a9fadd93041111.tar.xz
remove more warnings. move ROOT_COMPLEX selection to fam10
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/amdfam10/Kconfig1
-rw-r--r--src/northbridge/amd/amdfam10/amdfam10_conf.c12
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c3
-rw-r--r--src/northbridge/amd/lx/northbridge.c2
-rw-r--r--src/northbridge/amd/lx/northbridge.h11
-rw-r--r--src/northbridge/amd/lx/raminit.h4
-rw-r--r--src/northbridge/via/cn400/northbridge.c12
-rw-r--r--src/northbridge/via/cn400/vga.c4
8 files changed, 31 insertions, 18 deletions
diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
index 8e72c656fe..dd893f6bf8 100644
--- a/src/northbridge/amd/amdfam10/Kconfig
+++ b/src/northbridge/amd/amdfam10/Kconfig
@@ -21,6 +21,7 @@ config NORTHBRIDGE_AMD_AMDFAM10
bool
select HAVE_HIGH_TABLES
select HYPERTRANSPORT_PLUGIN_SUPPORT
+ select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
config AGP_APERTURE_SIZE
hex
diff --git a/src/northbridge/amd/amdfam10/amdfam10_conf.c b/src/northbridge/amd/amdfam10/amdfam10_conf.c
index df578044a6..567790cede 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_conf.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_conf.c
@@ -152,7 +152,7 @@ static u32 get_DctSelBaseAddr(u32 i)
return sel_m;
}
-
+#ifdef UNUSED_CODE
static void set_DctSelHiEn(u32 i, u32 val)
{
device_t dev;
@@ -168,6 +168,7 @@ static void set_DctSelHiEn(u32 i, u32 val)
pci_write_config32(dev, DRAM_CTRL_SEL_LOW, dcs_lo);
}
+#endif
static u32 get_DctSelHiEn(u32 i)
{
@@ -200,6 +201,7 @@ static void set_DctSelBaseOffset(u32 i, u32 sel_off_m)
}
+#ifdef UNUSED_CODE
static u32 get_DctSelBaseOffset(u32 i)
{
device_t dev;
@@ -215,6 +217,8 @@ static u32 get_DctSelBaseOffset(u32 i)
sel_off_m = dcs_hi>>(20+DCSH_DctSelBaseOffset_47_26_SHIFT-26);
return sel_off_m;
}
+#endif
+
#if CONFIG_AMDMCT == 0
static u32 get_one_DCT(struct mem_info *meminfo)
@@ -231,9 +235,8 @@ static u32 get_one_DCT(struct mem_info *meminfo)
return one_DCT;
}
-#endif
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
-
+// See that other copy in northbridge.c
static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes)
{
u32 ii;
@@ -313,7 +316,8 @@ static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes)
return carry_over;
}
-#endif
+#endif
+#endif // CONFIG_AMDMCT
#if CONFIG_EXT_CONF_SUPPORT
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index ab7be4e9e6..76d85f6c3c 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -795,7 +795,8 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
return mem_hole;
}
-
+// WHY this check? CONFIG_AMDMCT is enabled on all Fam10 boards.
+// Does it make sense not to?
#if CONFIG_AMDMCT == 0
static void disable_hoist_memory(unsigned long hole_startk, int i)
{
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index e7136dfdc9..137f7a9d09 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -77,9 +77,7 @@
extern void graphics_init(void);
extern void cpubug(void);
extern void chipsetinit(void);
-extern uint32_t get_systop(void);
-void northbridge_init_early(void);
void setup_realmode_idt(void);
void do_vsmbios(void);
diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h
index 560ab30612..99ea284b65 100644
--- a/src/northbridge/amd/lx/northbridge.h
+++ b/src/northbridge/amd/lx/northbridge.h
@@ -17,11 +17,16 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <cpu/amd/lxdef.h>
#ifndef NORTHBRIDGE_AMD_LX_H
#define NORTHBRIDGE_AMD_LX_H
-extern unsigned int lx_scan_root_bus(device_t root, unsigned int max);
+#include <cpu/amd/lxdef.h>
+
+/* northbridge.c */
+unsigned int lx_scan_root_bus(device_t root, unsigned int max);
int sizeram(void);
-#endif /* NORTHBRIDGE_AMD_LX_H */
+/* northbridgeinit.c */
+void northbridge_init_early(void);
+uint32_t get_systop(void);
+#endif
diff --git a/src/northbridge/amd/lx/raminit.h b/src/northbridge/amd/lx/raminit.h
index 4d6652f83b..b05b0edf5b 100644
--- a/src/northbridge/amd/lx/raminit.h
+++ b/src/northbridge/amd/lx/raminit.h
@@ -27,4 +27,6 @@ struct mem_controller {
uint16_t channel0[DIMM_SOCKETS];
};
-#endif /* RAMINIT_H */
+void sdram_initialize(int controllers, const struct mem_controller *ctrl);
+
+#endif
diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c
index f867427824..80dcc8d1a9 100644
--- a/src/northbridge/via/cn400/northbridge.c
+++ b/src/northbridge/via/cn400/northbridge.c
@@ -46,8 +46,8 @@ static void memctrl_init(device_t dev)
vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_CN400_VLINK, 0);
- /* Setup Low Memory Top */
- /* 0x47 == HA(32:25) */
+ /* Setup Low Memory Top */
+ /* 0x47 == HA(32:25) */
/* 0x84/85 == HA(31:20) << 4 | DRAM Granularity */
ranks = pci_read_config8(dev, 0x47);
reg16 = (((u16)(ranks - 1) << 9) & 0xFFF0) | 0x01F0;
@@ -175,6 +175,7 @@ static void ram_resource(device_t dev, unsigned long index,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
+#ifdef UNUSED_CODE
static void ram_reservation(device_t dev, unsigned long index,
unsigned long base, unsigned long size)
{
@@ -188,6 +189,7 @@ static void ram_reservation(device_t dev, unsigned long index,
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
+#endif
static void tolm_test(void *gp, struct device *dev, struct resource *new)
{
@@ -278,7 +280,7 @@ static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max)
return max;
}
-static const struct device_operations pci_domain_ops = {
+static struct device_operations pci_domain_ops = {
.read_resources = cn400_domain_read_resources,
.set_resources = cn400_domain_set_resources,
.enable_resources = enable_childrens_resources,
@@ -295,7 +297,7 @@ static void cpu_bus_noop(device_t dev)
{
}
-static const struct device_operations cpu_bus_ops = {
+static struct device_operations cpu_bus_ops = {
.read_resources = cpu_bus_noop,
.set_resources = cpu_bus_noop,
.enable_resources = cpu_bus_noop,
@@ -305,7 +307,7 @@ static const struct device_operations cpu_bus_ops = {
static void enable_dev(struct device *dev)
{
- printk(BIOS_SPEW, "In cn400 enable_dev for device %s.\n", dev_path(dev));
+ printk(BIOS_SPEW, "CN400: enable_dev for device %s.\n", dev_path(dev));
/* Set the operations if it is a special bus type. */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
diff --git a/src/northbridge/via/cn400/vga.c b/src/northbridge/via/cn400/vga.c
index ac222ff157..c71431c7c4 100644
--- a/src/northbridge/via/cn400/vga.c
+++ b/src/northbridge/via/cn400/vga.c
@@ -58,7 +58,7 @@ static void vga_init(device_t dev)
* This is for compatibility with the VGA ROM's BIOS callbacks.
*/
//memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000);
- memcpy(0xf0000, temp, 0x10000);
+ memcpy((void *)0xf0000, (void *)temp, 0x10000);
printk(BIOS_DEBUG, "Initializing VGA\n");
/* Set memory rate to 200 MHz. */
@@ -103,7 +103,7 @@ static void vga_init(device_t dev)
outb(reg8, SR_DATA);
/* Clear the BOCHS BIOS out of memory, so it doesn't confuse Linux. */
- memset(0xf0000, 0, 0x10000);
+ memset((void *)0xf0000, 0, 0x10000);
#ifdef DEBUG_CN400
printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));