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authorArthur Heymans <arthur@aheymans.xyz>2017-12-23 23:09:54 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-06-29 07:45:22 +0000
commite798e6a0b946fe5a3964bc38fb7783a219adf177 (patch)
treeaa95c831d094a6373042cfd347b942227224e24d /src/northbridge
parentb1d26f0e9261ec4070e8561406853fe5bddeb27c (diff)
downloadcoreboot-e798e6a0b946fe5a3964bc38fb7783a219adf177.tar.xz
sb/intel/i82801ix: Use the common ACPI pirq generator
For this to work the northbridge and lpc bridge device need acpi_name functions. TESTED on Thinkpad X200, a valid PIRQ routing in SSDT in /sys/firmware/acpi/tables/SSDT Change-Id: I62e520f53fa3f928a8e6f3b3cf33af2acdd53ed9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/gm45/acpi/hostbridge.asl3
-rw-r--r--src/northbridge/intel/gm45/northbridge.c17
2 files changed, 17 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl
index c674df50d5..afa7a61404 100644
--- a/src/northbridge/intel/gm45/acpi/hostbridge.asl
+++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl
@@ -228,6 +228,3 @@ Method (_CRS, 0, Serialized)
Return (MCRS)
}
-
-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
-#include "acpi/gm45_pci_irqs.asl"
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 4c42513bd0..663a9ff579 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -191,6 +191,22 @@ static void mch_domain_init(struct device *dev)
pci_write_config32(dev, PCI_COMMAND, reg32);
}
+static const char *northbridge_acpi_name(const struct device *dev)
+{
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ return "PCI0";
+
+ if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0)
+ return NULL;
+
+ switch (dev->path.pci.devfn) {
+ case PCI_DEVFN(0, 0):
+ return "MCHC";
+ }
+
+ return NULL;
+}
+
static struct device_operations pci_domain_ops = {
.read_resources = mch_domain_read_resources,
.set_resources = mch_domain_set_resources,
@@ -199,6 +215,7 @@ static struct device_operations pci_domain_ops = {
.scan_bus = pci_domain_scan_bus,
.write_acpi_tables = northbridge_write_acpi_tables,
.acpi_fill_ssdt_generator = generate_cpu_entries,
+ .acpi_name = northbridge_acpi_name,
};