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authorElyes HAOUAS <ehaouas@noos.fr>2020-01-07 20:06:08 +0100
committerNico Huber <nico.h@gmx.de>2020-01-10 15:25:12 +0000
commit0c9630eeff6851d855179b3588fee87fce356d34 (patch)
treecfcaa6edf979072bfa18677babcddc27a5de58c4 /src/northbridge
parent0f82c12f71f23f0699fb85a5fe768fba00963e7a (diff)
downloadcoreboot-0c9630eeff6851d855179b3588fee87fce356d34.tar.xz
nb/intel/{i945,sandybridge}/bootblock.c: Fix typo
Change-Id: I3def16c7bbf9d1997930832185beb8228ae163bd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38245 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i945/bootblock.c2
-rw-r--r--src/northbridge/intel/sandybridge/bootblock.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index 38564bded1..1f20150ebb 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -26,7 +26,7 @@ void bootblock_early_northbridge_init(void)
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
+ * CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c
index 74114963c3..b6ba395080 100644
--- a/src/northbridge/intel/sandybridge/bootblock.c
+++ b/src/northbridge/intel/sandybridge/bootblock.c
@@ -26,7 +26,7 @@ void bootblock_early_northbridge_init(void)
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
+ * CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.