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authorStefan Reinauer <stefan.reinauer@coreboot.org>2011-04-21 20:24:43 +0000
committerStefan Reinauer <stepan@openbios.org>2011-04-21 20:24:43 +0000
commit1d888a97849d68a7136da558c3697c7f2a8d898a (patch)
tree56044eeb39625a7fc3d040d9e496eda7f82f8c51 /src/northbridge
parent305f2f50abe0360b10f2fef3d65a102912dade40 (diff)
downloadcoreboot-1d888a97849d68a7136da558c3697c7f2a8d898a.tar.xz
some ifdef --> if fixes
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i82830/smihandler.c2
-rw-r--r--src/northbridge/intel/i82830/vga.c4
-rw-r--r--src/northbridge/intel/i945/raminit.c18
3 files changed, 12 insertions, 12 deletions
diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c
index 852c764608..f7c6b5af25 100644
--- a/src/northbridge/intel/i82830/smihandler.c
+++ b/src/northbridge/intel/i82830/smihandler.c
@@ -37,7 +37,7 @@ extern u32 mbi_len;
/* If YABEL is enabled and it's not running at 0x00000000, we have to add some
* offset to all our mbi object memory accesses
*/
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL && !CONFIG_YABEL_DIRECTHW
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL && !CONFIG_YABEL_DIRECTHW
#define OBJ_OFFSET CONFIG_YABEL_VIRTMEM_LOCATION
#else
#define OBJ_OFFSET 0x00000
diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c
index 21c677960e..c82c484a3a 100644
--- a/src/northbridge/intel/i82830/vga.c
+++ b/src/northbridge/intel/i82830/vga.c
@@ -25,7 +25,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cbfs.h>
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#include <x86emu/x86emu.h>
#endif
@@ -62,7 +62,7 @@ static void vga_init(device_t dev)
printk(BIOS_INFO, "Graphics Initialization Complete\n");
/* Enable TV-Out */
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#define PIPE_A_CRT (1 << 0)
#define PIPE_A_LFP (1 << 1)
#define PIPE_A_TV (1 << 3)
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index a9e4a910e2..a7fbaa4439 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -113,7 +113,7 @@ void sdram_dump_mchbar_registers(void)
static int memclk(void)
{
int offset = 0;
-#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
+#if CONFIG_NORTHBRIDGE_INTEL_I945GM
offset++;
#endif
switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
@@ -125,7 +125,7 @@ static int memclk(void)
return -1;
}
-#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
+#if CONFIG_NORTHBRIDGE_INTEL_I945GM
static u16 fsbclk(void)
{
switch (MCHBAR32(CLKCFG) & 7) {
@@ -136,7 +136,7 @@ static u16 fsbclk(void)
}
return 0xffff;
}
-#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
+#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
static u16 fsbclk(void)
{
switch (MCHBAR32(CLKCFG) & 7) {
@@ -1075,7 +1075,7 @@ static const u32 *slew_group_lookup(int dual_channel, int index)
return nc;
}
-#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
+#if CONFIG_NORTHBRIDGE_INTEL_I945GM
/* Strength multiplier tables */
static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
@@ -1130,7 +1130,7 @@ static const u8 single_channel_strength_multiplier[] = {
0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
};
-#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
+#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
@@ -2186,7 +2186,7 @@ static void sdram_program_clock_crossing(void)
/**
* We add the indices according to our clocks from CLKCFG.
*/
-#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
+#if CONFIG_NORTHBRIDGE_INTEL_I945GM
static const u32 data_clock_crossing[] = {
0x00100401, 0x00000000, /* DDR400 FSB400 */
0xffffffff, 0xffffffff, /* nonexistant */
@@ -2231,7 +2231,7 @@ static void sdram_program_clock_crossing(void)
0xffffffff, 0xffffffff, /* nonexistant */
};
-#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
+#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
/* i945 G/P */
static const u32 data_clock_crossing[] = {
0xffffffff, 0xffffffff, /* nonexistant */
@@ -2822,9 +2822,9 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
{
u8 clocks[2] = { 0, 0 };
-#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
+#if CONFIG_NORTHBRIDGE_INTEL_I945GM
#define CLOCKS_WIDTH 2
-#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
+#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
#define CLOCKS_WIDTH 3
#endif
if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)