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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-08-14 15:20:42 -0500
committerMartin Roth <martinroth@google.com>2015-12-18 19:51:44 +0100
commit1eaaa0e446b88e0ad60c4b6f68a022a9184f1df8 (patch)
tree05ec93f8500e92ee6f0bed893e2e994957ed8173 /src/northbridge
parent5f2bf6d02ddb82887a17c0b48ce8eb3a300f9c09 (diff)
downloadcoreboot-1eaaa0e446b88e0ad60c4b6f68a022a9184f1df8.tar.xz
southbridge/amd/sr5650: Add MCFG ACPI table support
As the southbridge largely controls the PCI[e] configuration space this patch moves the resource allocation from the northbridge to the southbridge when the extended configuration space region is enabled. Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12050 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 58507d0866..563f21b107 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -740,7 +740,10 @@ static void amdfam10_domain_read_resources(device_t dev)
if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) {
struct resource *res = new_resource(dev, 0xc0010058);
res->base = CONFIG_MMCONF_BASE_ADDRESS;
- res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
+ res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */
+ res->align = log2(res->size);
+ res->gran = log2(res->size);
+ res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */
res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;