diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-02-16 10:01:33 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-24 14:10:00 +0000 |
| commit | 2119d0ba4345a19b9db7dc13e36f3fa57f75d234 (patch) | |
| tree | aeeef324906730e350c338edb4f5704f20a95385 /src/northbridge | |
| parent | ebdf298ec2dd84810a37a4aac154200b2102b394 (diff) | |
| download | coreboot-2119d0ba4345a19b9db7dc13e36f3fa57f75d234.tar.xz | |
treewide: Capitalize 'CMOS'
Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/gm45/igd.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/early_init.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/early_init.c | 4 |
4 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index cfd067e044..28e93b858e 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -153,13 +153,13 @@ void igd_compute_ggc(sysinfo_t *const sysinfo) if (!sysinfo->enable_igd || (capid & (1 << (33 - 32)))) sysinfo->ggc = 0x0002; else { - /* 4 for 32MB, default if not set in cmos */ + /* 4 for 32MB, default if not set in CMOS */ u8 gfxsize = 4; /* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled, 2MB GTT + 2MB shadow GTT (0x0b00) else. */ get_option(&gfxsize, "gfx_uma_size"); - /* Handle invalid cmos settings */ + /* Handle invalid CMOS settings */ /* Only allow settings between 32MB and 352MB */ gfxsize = MIN(MAX(gfxsize, 4), 12); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 1deca3eeba..44d25846c2 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -161,7 +161,7 @@ static void i945_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); - /* vram size from cmos option */ + /* vram size from CMOS option */ if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) gfxsize = 2; /* 2 for 8MB */ /* make sure no invalid setting is used */ diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index c3cd380dc5..8f925f71d7 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -43,7 +43,7 @@ static void early_graphics_setup(void) pci_write_config8(D0F0, DEVEN, BOARD_DEVEN); - /* vram size from cmos option */ + /* vram size from CMOS option */ if (get_option(®8, "gfx_uma_size") != CB_SUCCESS) reg8 = 0; /* 0 for 8MB */ /* make sure no invalid setting is used */ diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 3520b88deb..fbcfadbd9c 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -56,8 +56,8 @@ void x4x_early_init(void) /* Enable internal GFX */ pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); - /* Set preallocated IGD size from cmos */ - u8 gfxsize = 6; /* 6 for 64MiB, default if not set in cmos */ + /* Set preallocated IGD size from CMOS */ + u8 gfxsize = 6; /* 6 for 64MiB, default if not set in CMOS */ get_option(&gfxsize, "gfx_uma_size"); if (gfxsize > 12) gfxsize = 6; |