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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-10-19 10:13:14 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-11-23 17:30:13 +0100 |
| commit | 33b535f15ded011c92cd1757408a3453a55b44bd (patch) | |
| tree | 67ae10671273ccb152d5462290afcd4aba2579d9 /src/northbridge | |
| parent | 5903a78e1e5aa28dc18e626df416b4076398763d (diff) | |
| download | coreboot-33b535f15ded011c92cd1757408a3453a55b44bd.tar.xz | |
sandy/ivy/nehalem: Remerge interrupt handling
On those chipsets the pins are just a legacy concept. Real interrupts are
messages on corresponding busses or some internal logic of chipset.
Hence interrupt routing isn't anymore board-specific (dependent on layout) but
depends only on configuration.
Rather than attempting to sync real config, ACPI and legacy descriptors, just
use the same interrupt routing per chipset covering all possible devices.
The only part which remains board-specific are LPC and PCI interrupts.
Interrupt balancing may suffer from such merge but:
a) Doesn't seem to be the case of this map on current systems
b) Almost all OS use MSI nowadays bypassing this stuff completely
c) If we want a good balancing we need to take into account that e.g.
wlan card may be placed in a different slot and so would require complicated
balancing on runtime. It's difficult to maintain with almost no benefit.
Change-Id: I9f63d1d338c5587ebac7a52093e5b924f6e5ca2d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7130
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/nehalem/acpi/hostbridge.asl | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/acpi/hostbridge.asl | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage_native.c | 1 |
3 files changed, 1 insertions, 6 deletions
diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl index e826bd6bca..79736bcafd 100644 --- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl +++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl @@ -343,6 +343,3 @@ Method (_CRS, 0, Serialized) Return (MCRS) } - -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/nehalem_pci_irqs.asl" diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 690c072e72..427927182d 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -378,6 +378,3 @@ Method (_CRS, 0, Serialized) Return (MCRS) } - -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/sandybridge_pci_irqs.asl" diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c index 67c64d7898..902d66d0b9 100644 --- a/src/northbridge/intel/sandybridge/romstage_native.c +++ b/src/northbridge/intel/sandybridge/romstage_native.c @@ -91,6 +91,7 @@ void main(unsigned long bist) timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3c); + southbridge_configure_default_intmap(); rcba_config(); post_code(0x3d); |