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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 23:32:44 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-12 10:09:12 +0000 |
| commit | 3ac92b7c93addd8e75096162f88e65a3a54fcab0 (patch) | |
| tree | e08cf6472b8c771b9020b4622bc99ac434e0ecf6 /src/northbridge | |
| parent | 317399366e039d6796ad721ebb5ac5b121d2582a (diff) | |
| download | coreboot-3ac92b7c93addd8e75096162f88e65a3a54fcab0.tar.xz | |
haswell: Automatically determine system type
Check the PCH's LPC device ID to know the system type instead of relying
on hardcoded numbers. The `get_pch_platform_type` function is MRC-safe.
Change-Id: Icfe7c2dccb7c7a178892ad3a2e34ca93b33b2bb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43124
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 42a2a56c66..40b7b879d1 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -51,6 +51,7 @@ void mainboard_romstage_entry(void) .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, + .system_type = get_pch_platform_type(), .tseg_size = CONFIG_SMM_TSEG_SIZE, .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), .max_ddr3_freq = 1600, |