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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-05-18 13:35:21 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-04 11:09:22 +0200 |
| commit | 50036324070be4336096c111918dc1e1a3ea69a3 (patch) | |
| tree | 4f38808af068ce0b3c4c923c9cd272a257524ec7 /src/northbridge | |
| parent | 206e157cc1922f0db8e92ecd23d9b76e493d2b4c (diff) | |
| download | coreboot-50036324070be4336096c111918dc1e1a3ea69a3.tar.xz | |
AGESA: Fix invalid use of CFG_ declarations
The declarations of CFG_ evaluate to correct values only when
included after the definitions of BLDCFG_ in buildOpts.c.
So we never have CFG_PLAT_NUM_IO_APICS defined here.
Change-Id: I94b3dee5a3207b37921eb24a0bcd73b5a217b2d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14887
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/agesa/family15/northbridge.c | 10 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family15rl/northbridge.c | 10 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family15tn/northbridge.c | 10 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family16kb/northbridge.c | 10 |
4 files changed, 20 insertions, 20 deletions
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index c283103868..0079a7803b 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1081,11 +1081,11 @@ static void cpu_bus_scan(device_t dev) * This is needed because many IO-APIC devices only have 4 bits * for their APIC id and therefore must reside at 0..15 */ -#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */ -#define CFG_PLAT_NUM_IO_APICS 3 -#endif - if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) { - lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max; + + u8 plat_num_io_apics = 3; /* FIXME */ + + if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { + lapicid_start = (plat_num_io_apics - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); } diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 37bca386fc..511b34e49b 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -1071,11 +1071,11 @@ static void cpu_bus_scan(device_t dev) * This is needed because many IO-APIC devices only have 4 bits * for their APIC id and therefore must reside at 0..15 */ -#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */ -#define CFG_PLAT_NUM_IO_APICS 3 -#endif - if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) { - lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max; + + u8 plat_num_io_apics = 3; /* FIXME */ + + if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { + lapicid_start = (plat_num_io_apics - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); } diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 50afe73e46..576334d28e 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -1070,11 +1070,11 @@ static void cpu_bus_scan(device_t dev) * This is needed because many IO-APIC devices only have 4 bits * for their APIC id and therefore must reside at 0..15 */ -#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */ -#define CFG_PLAT_NUM_IO_APICS 3 -#endif - if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) { - lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max; + + u8 plat_num_io_apics = 3; /* FIXME */ + + if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { + lapicid_start = (plat_num_io_apics - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 15d81257be..25bb337b5d 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -1087,11 +1087,11 @@ static void cpu_bus_scan(device_t dev) * This is needed because many IO-APIC devices only have 4 bits * for their APIC id and therefore must reside at 0..15 */ -#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */ -#define CFG_PLAT_NUM_IO_APICS 3 -#endif - if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) { - lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max; + + u8 plat_num_io_apics = 3; /* FIXME */ + + if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { + lapicid_start = (plat_num_io_apics - 1) / core_max; lapicid_start = (lapicid_start + 1) * core_max; printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); } |