diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2017-03-23 18:53:38 +0100 |
---|---|---|
committer | Arthur Heymans <arthur@aheymans.xyz> | 2017-03-27 16:22:13 +0200 |
commit | 50db9c99be7e09aafb7cfd353bd0ac9878b76fca (patch) | |
tree | e21b4ff64d3cb138bcd0de680681bfe6eb93bae9 /src/northbridge | |
parent | aa206478cbf1aff3ec574f5b91f2f24e96a56fee (diff) | |
download | coreboot-50db9c99be7e09aafb7cfd353bd0ac9878b76fca.tar.xz |
nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timings
This is a cosmetic change.
Change-Id: Iea4dd97e9d83594447427abd9f844e507b805192
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18960
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r-- | src/northbridge/intel/sandybridge/raminit_ivy.c | 20 | ||||
-rw-r--r-- | src/northbridge/intel/sandybridge/raminit_sandy.c | 20 |
2 files changed, 20 insertions, 20 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 9349cf772f..f13d61375a 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -210,7 +210,7 @@ static void dram_timing(ramctr_timing * ctrl) printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32); /* Find CAS latency */ - val = (ctrl->tAA + ctrl->tCK - 1) / ctrl->tCK; + val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); printk(BIOS_DEBUG, "Minimum CAS latency : %uT\n", val); /* Find lowest supported CAS latency that satisfies the minimum value */ while (!((ctrl->cas_supported >> (val - MIN_CAS)) & 1) @@ -234,38 +234,38 @@ static void dram_timing(ramctr_timing * ctrl) printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); /* Find tRCD */ - ctrl->tRCD = (ctrl->tRCD + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); - ctrl->tRP = (ctrl->tRP + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); /* Find tRAS */ - ctrl->tRAS = (ctrl->tRAS + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); /* Find tWR */ - ctrl->tWR = (ctrl->tWR + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); /* Find tFAW */ - ctrl->tFAW = (ctrl->tFAW + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); /* Find tRRD */ - ctrl->tRRD = (ctrl->tRRD + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); /* Find tRTP */ - ctrl->tRTP = (ctrl->tRTP + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); /* Find tWTR */ - ctrl->tWTR = (ctrl->tWTR + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ - ctrl->tRFC = (ctrl->tRFC + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); ctrl->tREFI = get_REFI(ctrl->tCK); diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index a83cb359fb..84c237467f 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -210,7 +210,7 @@ static void dram_timing(ramctr_timing * ctrl) printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32); /* Find CAS latency */ - val = (ctrl->tAA + ctrl->tCK - 1) / ctrl->tCK; + val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); printk(BIOS_DEBUG, "Minimum CAS latency : %uT\n", val); /* Find lowest supported CAS latency that satisfies the minimum value */ while (!((ctrl->cas_supported >> (val - MIN_CAS)) & 1) @@ -234,38 +234,38 @@ static void dram_timing(ramctr_timing * ctrl) printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); /* Find tRCD */ - ctrl->tRCD = (ctrl->tRCD + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); - ctrl->tRP = (ctrl->tRP + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); /* Find tRAS */ - ctrl->tRAS = (ctrl->tRAS + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); /* Find tWR */ - ctrl->tWR = (ctrl->tWR + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); /* Find tFAW */ - ctrl->tFAW = (ctrl->tFAW + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); /* Find tRRD */ - ctrl->tRRD = (ctrl->tRRD + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); /* Find tRTP */ - ctrl->tRTP = (ctrl->tRTP + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); /* Find tWTR */ - ctrl->tWTR = (ctrl->tWTR + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ - ctrl->tRFC = (ctrl->tRFC + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK - 1); printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); ctrl->tREFI = get_REFI(ctrl->tCK); |