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authorJulius Werner <jwerner@chromium.org>2019-03-07 17:07:26 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-03-25 11:03:49 +0000
commit5d1f9a009647c741e8587015b14f1e852e1c489e (patch)
treeb6e87bac2f8a578b7bee6b73111e04bd3750eeb8 /src/northbridge
parent2de19038beffa154eefe40755b607aa9f94d9f9f (diff)
downloadcoreboot-5d1f9a009647c741e8587015b14f1e852e1c489e.tar.xz
Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few). Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c4
-rw-r--r--src/northbridge/amd/pi/agesawrapper.c2
-rw-r--r--src/northbridge/intel/i945/gma.c4
-rw-r--r--src/northbridge/intel/i945/raminit.c2
-rw-r--r--src/northbridge/intel/sandybridge/romstage.c2
5 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 16b7becccc..1d071c1877 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -177,7 +177,7 @@ static void ht_route_link(struct bus *link, scan_state mode)
pci_write_config32(link->dev, link->cap + 0x14, busses);
if (mode == HT_ROUTE_FINAL) {
- if (CONFIG_HT_CHAIN_DISTRIBUTE)
+ if (CONFIG(HT_CHAIN_DISTRIBUTE))
parent->subordinate = ALIGN_UP(link->subordinate, 8) - 1;
else
parent->subordinate = link->subordinate;
@@ -1450,7 +1450,7 @@ static void cpu_bus_scan(struct device *dev)
siblings = 3; //quad core
}
- disable_siblings = !CONFIG_LOGICAL_CPUS;
+ disable_siblings = !CONFIG(LOGICAL_CPUS);
#if CONFIG(LOGICAL_CPUS)
get_option(&disable_siblings, "multi_core");
#endif
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index 28f2876e95..1cc7b7c3d7 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -127,7 +127,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
// Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow
// the compiler to flag the error if CONFIG_GFXUMA is not set.
- PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE;
+ PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE;
PostParams->MemConfig.UmaSize = 0;
PostParams->MemConfig.BottomIo = (UINT16)
(CONFIG_BOTTOMIO_POSITION >> 24);
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index ee656de66a..9c4f410d02 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -677,10 +677,10 @@ static void gma_ngi(struct device *const dev)
if (err == 0)
gfx_set_init_done(1);
/* Linux relies on VBT for panel info. */
- if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) {
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CALISTOGA");
}
- if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) {
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT LAKEPORT-G");
}
}
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 05b577787d..be3d17a2fd 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -284,7 +284,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
/* clear self refresh status if check is disabled or not a resume */
- if (!CONFIG_CHECK_SLFRCS_ON_RESUME
+ if (!CONFIG(CHECK_SLFRCS_ON_RESUME)
|| sysinfo->boot_path != BOOT_PATH_RESUME) {
MCHBAR8(SLFRCS) |= 3;
} else {
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index b49165cb3f..7465080bbf 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -67,7 +67,7 @@ void mainboard_romstage_entry(unsigned long bist)
mainboard_config_superio();
/* USB is initialized in MRC if MRC is used. */
- if (CONFIG_USE_NATIVE_RAMINIT) {
+ if (CONFIG(USE_NATIVE_RAMINIT)) {
early_usb_init(mainboard_usb_ports);
}