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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-18 20:12:13 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-18 20:12:13 +0000 |
| commit | 607614d0a9cb589c914d92c1b8957b8141dcaf8e (patch) | |
| tree | 76cd959e4051eafe99a8fc2b9fbd27c85acdbb93 /src/northbridge | |
| parent | 24f324cb855b77db17b543feed72a03da0e06bc6 (diff) | |
| download | coreboot-607614d0a9cb589c914d92c1b8957b8141dcaf8e.tar.xz | |
Fix/drop some obsolete comments,
- s/Options.lb/devicetree.cb/
- s/Config.lb/devicetree.cb/
- s/cache_as_ram_auto.c/romstage.c/
- h8dmr_fam10/README: Drop obsolete comment, we have mc_patch_01000086.h in
the tree now.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdk8/northbridge.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/lx/grphinit.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 1f98684c6b..c7bf4919fb 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1,6 +1,6 @@ /* This should be done by Eric 2004.12 yhlu add dual core support - 2005.01 yhlu add support move apic before pci_domain in MB Config.lb + 2005.01 yhlu add support move apic before pci_domain in MB devicetree.cb 2005.02 yhlu add e0 memory hole support 2005.11 yhlu add put sb ht chain on bus 0 */ diff --git a/src/northbridge/amd/lx/grphinit.c b/src/northbridge/amd/lx/grphinit.c index b245eea062..c6ab4df93a 100644 --- a/src/northbridge/amd/lx/grphinit.c +++ b/src/northbridge/amd/lx/grphinit.c @@ -85,7 +85,7 @@ void graphics_init(void) * Controller Priority Select(11) 1, Primary * Display Select(10:8) 0x0, CRT * Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1, - * defined in mainboard/../Options.lb + * defined in devicetree.cb * PLL Reference Clock Bypass(0) 0, Default */ diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index e301f8a019..53d0d8c42c 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -570,7 +570,7 @@ static void i945_setup_pci_express_x16(void) /* Setup SLOTCAP */ /* TODO: These values are mainboard dependent and should - * be set from Config.lb or Options.lb. + * be set from devicetree.cb. */ /* NOTE: SLOTCAP becomes RO after the first write! */ reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xb4); |