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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-04-19 19:57:01 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-05-27 13:54:47 +0200 |
commit | 70d92b9465b1edf646b25b89f1442f7107b5f1f6 (patch) | |
tree | 8d0a39990358f3fd92b00f0e790b7667ca90fd1c /src/northbridge | |
parent | ef8bb9136e9371753e50cb15b334c9d0f5c70930 (diff) | |
download | coreboot-70d92b9465b1edf646b25b89f1442f7107b5f1f6.tar.xz |
CBMEM: Clarify CBMEM_TOP_BACKUP function usage
The deprecated LATE_CBMEM_INIT function is renamed:
set_top_of_ram -> set_late_cbmem_top
Obscure term top_of_ram is replaced:
backup_top_of_ram -> backup_top_of_low_cacheable
get_top_of_ram -> restore_top_of_low_cacheable
New function that always resolves to CBMEM top boundary, with
or without SMM, is named restore_cbmem_top().
Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r-- | src/northbridge/amd/agesa/agesawrapper.c | 2 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/northbridge.c | 4 | ||||
-rw-r--r-- | src/northbridge/amd/gx2/northbridge.c | 2 | ||||
-rw-r--r-- | src/northbridge/amd/lx/northbridge.c | 4 | ||||
-rw-r--r-- | src/northbridge/amd/lx/northbridgeinit.c | 2 | ||||
-rw-r--r-- | src/northbridge/amd/pi/agesawrapper.c | 4 | ||||
-rw-r--r-- | src/northbridge/amd/pi/ramtop.c | 4 | ||||
-rw-r--r-- | src/northbridge/intel/e7505/northbridge.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/e7505/raminit.c | 4 | ||||
-rw-r--r-- | src/northbridge/intel/i3100/northbridge.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/i440bx/northbridge.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/i5000/northbridge.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/i82810/northbridge.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/i82830/northbridge.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/i855/northbridge.c | 2 | ||||
-rw-r--r-- | src/northbridge/via/cn700/northbridge.c | 2 | ||||
-rw-r--r-- | src/northbridge/via/cx700/northbridge.c | 2 | ||||
-rw-r--r-- | src/northbridge/via/vx900/early_vx900.c | 6 | ||||
-rw-r--r-- | src/northbridge/via/vx900/northbridge.c | 2 |
19 files changed, 26 insertions, 26 deletions
diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c index 079625671a..7668a089a6 100644 --- a/src/northbridge/amd/agesa/agesawrapper.c +++ b/src/northbridge/amd/agesa/agesawrapper.c @@ -111,7 +111,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) status = AmdInitPost(PostParams); AGESA_EVENTLOG(status, &PostParams->StdHeader); - backup_top_of_ram(PostParams->MemConfig.Sub4GCacheTop); + backup_top_of_low_cacheable(PostParams->MemConfig.Sub4GCacheTop); AmdReleaseStruct(&AmdParamStruct); diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 02d5560d12..c957af0095 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -999,10 +999,10 @@ static void amdk8_domain_set_resources(device_t dev) } #if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); + set_late_cbmem_top(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #else - set_top_of_ram(ramtop); + set_late_cbmem_top(ramtop); #endif assign_resources(dev->link_list); diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index 5c49f1add3..ef3b30a80d 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -286,7 +286,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); /* Systop - 0xc0000 -> KB */ - set_top_of_ram(tomk * 1024); + set_late_cbmem_top(tomk * 1024); } assign_resources(dev->link_list); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index f0304becef..93ec3502e0 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -358,14 +358,14 @@ static void pci_domain_set_resources(device_t dev) mc_dev = dev->link_list->children; if (mc_dev) { - tomk = get_top_of_ram() / 1024; + tomk = restore_top_of_low_cacheable() / 1024; /* Report the memory regions All memory up to systop except 0xa0000-0xbffff */ idx = 10; ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); // Systop - 0xc0000 -> KB - set_top_of_ram(tomk * 1024); + set_late_cbmem_top(tomk * 1024); } assign_resources(dev->link_list); diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 6c48fb4155..f588ead56a 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -710,7 +710,7 @@ static void setup_lx_cache(void) wbinvd(); } -unsigned long get_top_of_ram(void) +uintptr_t restore_top_of_low_cacheable(void) { uint32_t systop; msr_t msr; diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index ec1d0acf9f..d4b9984f81 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -153,9 +153,9 @@ AGESA_STATUS agesawrapper_amdinitpost(void) * UMA may or may not be cacheable, so Sub4GCacheTop could be * higher than UmaBase. With UMA_NONE we see UmaBase==0. */ if (PostParams->MemConfig.UmaBase) - backup_top_of_ram(PostParams->MemConfig.UmaBase << 16); + backup_top_of_low_cacheable(PostParams->MemConfig.UmaBase << 16); else - backup_top_of_ram(PostParams->MemConfig.Sub4GCacheTop); + backup_top_of_low_cacheable(PostParams->MemConfig.Sub4GCacheTop); printk( BIOS_SPEW, diff --git a/src/northbridge/amd/pi/ramtop.c b/src/northbridge/amd/pi/ramtop.c index 2b501dcf05..8fa81c715a 100644 --- a/src/northbridge/amd/pi/ramtop.c +++ b/src/northbridge/amd/pi/ramtop.c @@ -19,13 +19,13 @@ #define CBMEM_TOP_SCRATCHPAD 0x78 -void backup_top_of_ram(uint64_t ramtop) +void backup_top_of_low_cacheable(uintptr_t ramtop) { uint16_t top_cache = ramtop >> 16; pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache); } -unsigned long get_top_of_ram(void) +uintptr_t restore_top_of_low_cacheable(void) { uint16_t top_cache; top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD); diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 71b19f6cf2..f6e14d67f7 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -92,7 +92,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } - set_top_of_ram(tolmk * 1024); + set_late_cbmem_top(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 9adbca1a30..975a373433 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -1892,10 +1892,10 @@ void e7505_mch_init(const struct mem_controller *memctrl) sdram_enable(memctrl); } -unsigned long get_top_of_ram(void) +uintptr_t restore_top_of_low_cacheable(void) { u32 tolm = (pci_read_config16(MCHDEV, TOLM) & ~0x7ff) << 16; - return (unsigned long) tolm; + return tolm; } /** diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 3663c11370..f05eea0464 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -119,7 +119,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } - set_top_of_ram(tolmk * 1024); + set_late_cbmem_top(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index b8b8394da8..dba7880d7f 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -67,7 +67,7 @@ static void i440bx_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); - set_top_of_ram(tomk * 1024); + set_late_cbmem_top(tomk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index 083e4c9a47..f54ab5ed35 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -107,7 +107,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - set_top_of_ram(tolm); + set_late_cbmem_top(tolm); } static struct pci_operations intel_pci_ops = { diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 41d0b44edd..2274c0f5e2 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -118,7 +118,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 768, tomk - 768); uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10); - set_top_of_ram(tomk_stolen * 1024); + set_late_cbmem_top(tomk_stolen * 1024); assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 5f196d5c51..ce9a3fbe0b 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -87,7 +87,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); - set_top_of_ram(tomk_stolen * 1024); + set_late_cbmem_top(tomk_stolen * 1024); } static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index bc497a89ef..3398d66ff4 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -101,7 +101,7 @@ static void pci_domain_set_resources(device_t dev) /* ram_resource(dev, idx++, 1024, tolmk - 1024); */ ram_resource(dev, idx++, 768, tolmk - 768); - set_top_of_ram(tomk * 1024); + set_late_cbmem_top(tomk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index 141ad150ad..2121162348 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -130,7 +130,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } - set_top_of_ram((tolmk - CONFIG_VIDEO_MB * 1024) * 1024); + set_late_cbmem_top((tolmk - CONFIG_VIDEO_MB * 1024) * 1024); /* Report the memory regions. */ idx = 10; diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index 670603bae3..19bdf11bac 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -65,7 +65,7 @@ static void pci_domain_set_resources(device_t dev) tolmk -= 1024; // TOP 1M SM Memory } - set_top_of_ram(tolmk * 1024); + set_late_cbmem_top(tolmk * 1024); /* Report the memory regions */ idx = 10; diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index 6e1bc23cae..b350ffde28 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -18,10 +18,10 @@ #include <arch/io.h> #include <console/console.h> -unsigned long get_top_of_ram(void) +uintptr_t restore_top_of_low_cacheable(void) { - u16 reg_tom = pci_read_config8(MCU, 0x88); - return (((unsigned long)reg_tom) << 24) - (256 << 20); + u8 reg_tom = pci_read_config8(MCU, 0x88); + return (reg_tom << 24) - 256 * MiB; } /** diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index 7429c4f973..fbb8fdf898 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -277,7 +277,7 @@ static void vx900_set_resources(device_t dev) u64 tor = vx900_remap_above_4g(mcu, pci_tolm); ram_resource(dev, idx++, RAM_4GB >> 10, (tor - RAM_4GB) >> 10); - set_top_of_ram(tolmk << 10); + set_late_cbmem_top(tolmk << 10); printk(BIOS_DEBUG, "======================================================\n"); assign_resources(dev->link_list); |