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| author | Martin Roth <martinroth@chromium.org> | 2019-04-22 16:14:12 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-02 14:32:41 +0000 |
| commit | 778c8a77c1fc468b320f3471e7e753fd6f4afed7 (patch) | |
| tree | 1fc0cb9f3799f7e54ab995c80aa9ef45bcfe018e /src/northbridge | |
| parent | d7e3ead8358ac76d432e26849951defb9ab28a9b (diff) | |
| download | coreboot-778c8a77c1fc468b320f3471e7e753fd6f4afed7.tar.xz | |
soc/amd/picasso: Stub out bootblock
Remove all Picasso bootblock support. CAR is not a supportable
feature, and the first code executed at the reset vector will be
a hybrid romstage. Details for this implementation may be found
in Documentation/soc/amd/picasso/family17h.md.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8edf45c02dc5bfcdca03abf1294db4be508682cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/northbridge')
0 files changed, 0 insertions, 0 deletions