diff options
| author | Philipp Deppenwiese <zaolin@das-labor.org> | 2018-02-27 19:40:52 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-06-04 20:33:07 +0000 |
| commit | c07f8fbe6fd13e4245da71574b52b47e9733db84 (patch) | |
| tree | 12db8b3c40552eab81045c6165538e2d3ba36ce8 /src/northbridge | |
| parent | 961d31bdb3c97e177156ed335d6f2c726d08ab51 (diff) | |
| download | coreboot-c07f8fbe6fd13e4245da71574b52b47e9733db84.tar.xz | |
security/tpm: Unify the coreboot TPM software stack
* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
* MAINBOARD_HAS_*_TPM # * BUS driver
* MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
* Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.
Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 0426b831e7..61f5e4a50c 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -28,7 +28,7 @@ #include <device/pci_def.h> #include <device/device.h> #include <halt.h> -#include <security/tpm/tis.h> +#include <security/tpm/tspi.h> #include <northbridge/intel/sandybridge/chip.h> #include "southbridge/intel/bd82x6x/pch.h" #include <southbridge/intel/common/gpio.h> @@ -117,9 +117,8 @@ void mainboard_romstage_entry(unsigned long bist) northbridge_romstage_finalize(s3resume); - if (IS_ENABLED(CONFIG_LPC_TPM)) { - init_tpm(s3resume); - } + if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) + tpm_setup(s3resume); post_code(0x3f); } |