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authorUwe Hermann <uwe@hermann-uwe.de>2007-06-19 22:47:11 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2007-06-19 22:47:11 +0000
commitdfb3c130d5cdd3a01531c23c3d15e7a1010bf221 (patch)
tree625092b43a0c3ac24fa359eb14df0f922f81e6ad /src/northbridge
parentc72ff11281233c097441e809a52b560b1a131196 (diff)
downloadcoreboot-dfb3c130d5cdd3a01531c23c3d15e7a1010bf221.tar.xz
Various minor cosmetics and coding style fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i82810/chip.h3
-rw-r--r--src/northbridge/intel/i82810/i82810.h28
-rw-r--r--src/northbridge/intel/i82810/northbridge.c64
-rw-r--r--src/northbridge/intel/i82810/raminit.c79
-rw-r--r--src/northbridge/intel/i82810/raminit.h11
5 files changed, 97 insertions, 88 deletions
diff --git a/src/northbridge/intel/i82810/chip.h b/src/northbridge/intel/i82810/chip.h
index 6187fde469..3e7e1eb0da 100644
--- a/src/northbridge/intel/i82810/chip.h
+++ b/src/northbridge/intel/i82810/chip.h
@@ -18,8 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-struct northbridge_intel_i82810_config
-{
+struct northbridge_intel_i82810_config {
};
extern struct chip_operations northbridge_intel_i82810_ops;
diff --git a/src/northbridge/intel/i82810/i82810.h b/src/northbridge/intel/i82810/i82810.h
index 0b406cead4..d5979787cb 100644
--- a/src/northbridge/intel/i82810/i82810.h
+++ b/src/northbridge/intel/i82810/i82810.h
@@ -34,26 +34,26 @@
* should not be touched.
*/
-#define VID 0x00 /* Vendor Identification */
-#define DID 0x02 /* Device Identification */
-#define PCICMD 0x04 /* PCI Command Register */
-#define PCISTS 0x06 /* PCI Status Register */
-#define RID 0x08 /* Revision Identification */
-#define SUBC 0x0a /* Sub-Class Code */
-#define BCC 0x0b /* Base Class Code */
-#define MLT 0x0d /* Master Latency Timer */
-#define HDR 0x0e /* Header Type */
-#define SVID 0x2c /* Subsystem Vendor Identification */
-#define SID 0x2e /* Subsystem Identification */
-#define CAPPTR 0x34 /* Capabilities Pointer */
+#define VID 0x00 /* Vendor Identification */
+#define DID 0x02 /* Device Identification */
+#define PCICMD 0x04 /* PCI Command Register */
+#define PCISTS 0x06 /* PCI Status Register */
+#define RID 0x08 /* Revision Identification */
+#define SUBC 0x0a /* Sub-Class Code */
+#define BCC 0x0b /* Base Class Code */
+#define MLT 0x0d /* Master Latency Timer */
+#define HDR 0x0e /* Header Type */
+#define SVID 0x2c /* Subsystem Vendor Identification */
+#define SID 0x2e /* Subsystem Identification */
+#define CAPPTR 0x34 /* Capabilities Pointer */
-/* TODO: Descriptions */
+/* TODO: Descriptions. */
#define GMCHCFG 0x50
#define PAM 0x51
#define DRP 0x52
#define DRAMT 0x53
#define FDHC 0x58
-#define SMRAM 0x70 /* System Management RAM Control */
+#define SMRAM 0x70 /* System Management RAM Control */
#define MISSC 0x72
#define MISSC2 0x80
#define BUFF_SC 0x92
diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c
index 9758be39f7..29ace6e776 100644
--- a/src/northbridge/intel/i82810/northbridge.c
+++ b/src/northbridge/intel/i82810/northbridge.c
@@ -31,24 +31,24 @@
#include "northbridge.h"
#include "i82810.h"
-static void northbridge_init(device_t dev)
+static void northbridge_init(device_t dev)
{
printk_spew("Northbridge init\n");
}
static struct device_operations northbridge_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = northbridge_init,
- .enable = 0,
- .ops_pci = 0,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = northbridge_init,
+ .enable = 0,
+ .ops_pci = 0,
};
static struct pci_driver northbridge_driver __pci_driver = {
- .ops = &northbridge_operations,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x7120,
+ .ops = &northbridge_operations,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x7120,
};
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
@@ -62,16 +62,18 @@ static void pci_domain_read_resources(device_t dev)
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->base = 0x400;
resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ resource->flags =
+ IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ resource->flags =
+ IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index,
- unsigned long basek, unsigned long sizek)
+ unsigned long basek, unsigned long sizek)
{
struct resource *resource;
@@ -79,10 +81,10 @@ static void ram_resource(device_t dev, unsigned long index,
return;
}
resource = new_resource(dev, index);
- resource->base = ((resource_t)basek) << 10;
- resource->size = ((resource_t)sizek) << 10;
- resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+ resource->base = ((resource_t) basek) << 10;
+ resource->size = ((resource_t) sizek) << 10;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static void tolm_test(void *gp, struct device *dev, struct resource *new)
@@ -101,7 +103,8 @@ static uint32_t find_pci_tolm(struct bus *bus)
struct resource *min;
uint32_t tolm;
min = 0;
- search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
+ search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
+ &min);
tolm = 0xffffffffUL;
if (min && tolm > min->base) {
tolm = min->base;
@@ -143,7 +146,7 @@ static void pci_domain_set_resources(device_t dev)
/* Translate it to MB and add to tomk. */
tomk = (unsigned long)(translate_i82810_to_mb[drp_value & 0xf]);
/* Now do the same for DIMM 1. */
- drp_value = drp_value >> 4; // >>= 4; //? mess with later
+ drp_value = drp_value >> 4; // >>= 4; //? mess with later
tomk += (unsigned long)(translate_i82810_to_mb[drp_value]);
printk_debug("Setting RAM size to %d MB\n", tomk);
@@ -173,11 +176,11 @@ static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
}
static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
- .scan_bus = pci_domain_scan_bus,
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = enable_childrens_resources,
+ .init = 0,
+ .scan_bus = pci_domain_scan_bus,
};
static void cpu_bus_init(device_t dev)
@@ -190,11 +193,11 @@ static void cpu_bus_noop(device_t dev)
}
static struct device_operations cpu_bus_ops = {
- .read_resources = cpu_bus_noop,
- .set_resources = cpu_bus_noop,
- .enable_resources = cpu_bus_noop,
- .init = cpu_bus_init,
- .scan_bus = 0,
+ .read_resources = cpu_bus_noop,
+ .set_resources = cpu_bus_noop,
+ .enable_resources = cpu_bus_noop,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
};
static void enable_dev(struct device *dev)
@@ -205,8 +208,7 @@ static void enable_dev(struct device *dev)
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
pci_set_method(dev);
- }
- else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+ } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index 8ebb25f89c..f0d5cb71e6 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -47,9 +47,9 @@ Macros and definitions.
#endif
/* DRAMT[7:5] - SDRAM Mode Select (SMS). */
-#define RAM_COMMAND_SELF_REFRESH 0x0 /* IE disable refresh */
-#define RAM_COMMAND_NORMAL 0x1 /* Normal refresh, 15.6us/11.7us for 100/133MHz */
-#define RAM_COMMAND_NORMAL_FR 0x2 /* Fast refresh, 7.8us/5.85us for 100/133MHz */
+#define RAM_COMMAND_SELF_REFRESH 0x0 /* IE disable refresh */
+#define RAM_COMMAND_NORMAL 0x1 /* Normal refresh, 15.6us/11.7us for 100/133MHz */
+#define RAM_COMMAND_NORMAL_FR 0x2 /* Fast refresh, 7.8us/5.85us for 100/133MHz */
#define RAM_COMMAND_NOP 0x4
#define RAM_COMMAND_PRECHARGE 0x5
#define RAM_COMMAND_MRS 0x6
@@ -86,7 +86,7 @@ static void do_ram_command(const struct mem_controller *ctrl, uint32_t command,
PRINT_DEBUG(" Sending RAM command 0x");
PRINT_DEBUG_HEX8(reg);
PRINT_DEBUG(" to 0x");
- PRINT_DEBUG_HEX32(0 + addr_offset); // FIXME
+ PRINT_DEBUG_HEX32(0 + addr_offset); // FIXME
PRINT_DEBUG("\r\n");
/* Read from (DIMM start address + addr_offset). */
@@ -98,7 +98,8 @@ static void do_ram_command(const struct mem_controller *ctrl, uint32_t command,
DIMM-independant configuration functions.
-----------------------------------------------------------------------------*/
-static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_offset)
+static void spd_set_dram_size(const struct mem_controller *ctrl,
+ uint32_t row_offset)
{
/* The variables drp and dimm_size have to be ints since all the
* SMBus-related functions return ints, and its just easier this way.
@@ -106,9 +107,8 @@ static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_of
int i, drp, dimm_size;
drp = 0x00;
-
- for (i = 0; i < DIMM_SOCKETS; i++)
- {
+
+ for (i = 0; i < DIMM_SOCKETS; i++) {
/* First check if a DIMM is actually present. */
if (smbus_read_byte(ctrl->channel0[i], 2) == 4) {
print_debug("Found DIMM in slot ");
@@ -126,37 +126,45 @@ static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_of
* side. This will fail if the DIMM uses a
* non-supported DRAM tech, and can't be used until
* buffers are done dynamically.
- * Note: the factory BIOS just dies if it spots
- * this :D
+ * Note: the factory BIOS just dies if it spots this :D
*/
- if(dimm_size > 32) {
- print_err("DIMM row sizes larger than 128MB not"
- "supported on i810\r\n");
- print_err("Attempting to treat as 128MB DIMM\r\n");
+ if (dimm_size > 32) {
+ print_err("DIMM row sizes larger than 128MB not"
+ "supported on i810\r\n");
+ print_err
+ ("Attempting to treat as 128MB DIMM\r\n");
dimm_size = 32;
}
- /* Set the row offset, in KBytes (should this be Kbits?) */
- /* Note that this offset is the start of the next row. */
+ /* Set the row offset, in KBytes (should this be
+ * Kbits?). Note that this offset is the start of the
+ * next row.
+ */
row_offset = (dimm_size * 4 * 1024);
- /* This is the way I was doing this, it's provided mainly
- * as an alternative to the "new" way.
+ /* This is the way I was doing this, it's provided
+ * mainly as an alternative to the "new" way.
*/
- #if 0
+#if 0
/* 8MB */
- if(dimm_size == 0x2) dimm_size = 0x1;
+ if (dimm_size == 0x2)
+ dimm_size = 0x1;
/* 16MB */
- else if(dimm_size == 0x4) dimm_size = 0x4;
+ else if (dimm_size == 0x4)
+ dimm_size = 0x4;
/* 32MB */
- else if(dimm_size == 0x8) dimm_size = 0x7;
+ else if (dimm_size == 0x8)
+ dimm_size = 0x7;
/* 64 MB */
- else if(dimm_size == 0x10) dimm_size = 0xa;
+ else if (dimm_size == 0x10)
+ dimm_size = 0xa;
/* 128 MB */
- else if(dimm_size == 0x20) dimm_size = 0xd;
- else print_debug("Ram Size not supported\r\n");
- #endif
+ else if (dimm_size == 0x20)
+ dimm_size = 0xd;
+ else
+ print_debug("Ram Size not supported\r\n");
+#endif
/* This array is provided in raminit.h, because it got
* extremely messy. The above way is cleaner, but
@@ -169,8 +177,9 @@ static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_of
print_debug("\r\n");
/* If the DIMM is dual-sided, the DRP value is +2 */
- /* TODO: Figure out asymetrical configurations */
- if ((smbus_read_byte(ctrl->channel0[i], 127) | 0xf) == 0xff) {
+ /* TODO: Figure out asymetrical configurations. */
+ if ((smbus_read_byte(ctrl->channel0[i], 127) | 0xf) ==
+ 0xff) {
print_debug("DIMM is dual-sided\r\n");
dimm_size += 2;
}
@@ -179,7 +188,7 @@ static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_of
print_debug_hex8(i);
print_debug("\r\n");
- /* If there's no DIMM in the slot, set the value to 0. */
+ /* If there's no DIMM in the slot, set value to 0. */
dimm_size = 0x00;
}
@@ -233,11 +242,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
* 10 = Write Only
* 11 = Read/Write
- * Bit Range
- * 7:6 000F0000 - 000FFFFF
- * 5:4 000E0000 - 000EFFFF
- * 3:2 000D0000 - 000DFFFF
- * 1:0 000C0000 - 000CFFFF
+ * Bit Range
+ * 7:6 000F0000 - 000FFFFF
+ * 5:4 000E0000 - 000EFFFF
+ * 3:2 000D0000 - 000DFFFF
+ * 1:0 000C0000 - 000CFFFF
*/
/* Ideally, this should be R/W for as many ranges as possible. */
@@ -293,7 +302,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
*/
uint32_t row_offset;
- spd_set_dram_size(ctrl, row_offset);
+ spd_set_dram_size(ctrl, row_offset);
/* 1. Apply NOP. */
PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
diff --git a/src/northbridge/intel/i82810/raminit.h b/src/northbridge/intel/i82810/raminit.h
index 43edd837d6..08d9a63908 100644
--- a/src/northbridge/intel/i82810/raminit.h
+++ b/src/northbridge/intel/i82810/raminit.h
@@ -21,7 +21,7 @@
#ifndef NORTHBRIDGE_INTEL_I82810_RAMINIT_H
#define NORTHBRIDGE_INTEL_I82810_RAMINIT_H
-/* The i810 supports max 2 dual-sided DIMMs. */
+/* The 82810 supports max. 2 dual-sided DIMMs. */
#define DIMM_SOCKETS 2
struct mem_controller {
@@ -29,9 +29,6 @@ struct mem_controller {
uint16_t channel0[DIMM_SOCKETS];
};
-
-#endif /* NORTHBRIDGE_INTEL_I82810_RAMINIT_H */
-
/* The following table has been bumped over to this header to avoid clutter in
* raminit.c. It's used to translate the value read from SPD Byte 31 to a value
* the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most
@@ -40,7 +37,7 @@ struct mem_controller {
* this table is necessary.
*/
-/* TODO: Find a better way of doing this */
+/* TODO: Find a better way of doing this. */
static const uint8_t translate_spd_to_i82810[] = {
/* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB
@@ -86,5 +83,7 @@ static const uint8_t translate_spd_to_i82810[] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, /* 0x31-3f Invalid */
0x0f, /* 0x40 256/0 or 256 */
- /* Anything larger is not supported by the i810 */
+ /* Anything larger is not supported by the 82810. */
};
+
+#endif /* NORTHBRIDGE_INTEL_I82810_RAMINIT_H */