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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-07 23:23:13 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-09 23:47:13 +0000 |
| commit | ea1953f492e2ed80cd39f865e8320debf49324d0 (patch) | |
| tree | 6d50bdc4135b77f2a3ee9305a56b143227a71c20 /src/northbridge | |
| parent | cdee5e9d12da6109e30917f81bcfa2310bde8863 (diff) | |
| download | coreboot-ea1953f492e2ed80cd39f865e8320debf49324d0.tar.xz | |
nb/intel/ironlake/raminit.c: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I36500c1f0eb3c37d08c691d22382ceca732d1355
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/ironlake/raminit.c | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 13f0c35231..f1f8aa5e9a 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3652,12 +3652,6 @@ void chipset_init(const int s3resume) MCHBAR8(0x2ca8) = 0; system_reset(); } -#if 0 - if (!s3resume) { - pre_raminit_3(x2ca8); - } - pre_raminit_4a(x2ca8); -#endif dmi_setup(); @@ -3851,10 +3845,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap) collect_system_info(&info); calculate_timings(&info); -#if 0 - pci_write_config8(NORTHBRIDGE, 0xdf, 0x82); -#endif - if (!s3resume) { u8 reg8 = pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); if (x2ca8 == 0 && (reg8 & 0x80)) { @@ -4583,7 +4573,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap) MCHBAR8_OR(0xff4, 0x2); MCHBAR32_AND_OR(0xff8, ~0xe008, 0x1020); -#if 1 MCHBAR32(0xd00) = IOMMU_BASE2 | 1; MCHBAR32(0xd40) = IOMMU_BASE1 | 1; MCHBAR32(0xdc0) = IOMMU_BASE4 | 1; @@ -4592,18 +4581,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write32p(IOMMU_BASE2 | 0xffc, 0xc0000000); write32p(IOMMU_BASE4 | 0xffc, 0x80000000); -#else - { - u32 eax; - // = 0xe911714b - eax = read32p(0xffc + (MCHBAR32(0xd00) & ~1)) | 0x08000000; - write32p(0xffc + (MCHBAR32(0xd00) & ~1), eax); - // = 0xe911714b - eax = read32p(0xffc + (MCHBAR32(0xdc0) & ~1)) | 0x40000000; - write32p(0xffc + (MCHBAR32(0xdc0) & ~1), eax); - } -#endif - { u32 eax; |