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| author | Edwin Beasant <edwin_beasant@virtensys.com> | 2010-07-06 21:05:04 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2010-07-06 21:05:04 +0000 |
| commit | eb50c7d922e91f0247b3705eccb2d2eec638c277 (patch) | |
| tree | 2def570d089b2f6deb2beac165e18756a578e308 /src/northbridge | |
| parent | 8376831eafc1be1175529fd21e0d2fe40339d4eb (diff) | |
| download | coreboot-eb50c7d922e91f0247b3705eccb2d2eec638c277.tar.xz | |
Re-integrate "USE_OPTION_TABLE" code.
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdk8/coherent_ht.c | 4 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit.c | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/raminit.c | 3 |
3 files changed, 7 insertions, 8 deletions
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 1b0feb123a..293abc7067 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -68,6 +68,7 @@ #include <device/hypertransport_def.h> #include <stdlib.h> #include "arch/romcc_io.h" +#include <pc80/mc146818rtc.h> #include "amdk8.h" @@ -1594,8 +1595,7 @@ static void coherent_ht_finalize(unsigned nodes) #if CONFIG_LOGICAL_CPUS==1 unsigned total_cpus; - if ((!CONFIG_HAVE_OPTION_TABLE) || - read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */ + if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */ total_cpus = verify_dualcore(nodes); } else { diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 7ad1b8004c..8217464e37 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -549,8 +549,7 @@ static void hw_enable_ecc(const struct mem_controller *ctrl) if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn; } - if (CONFIG_HAVE_OPTION_TABLE && - read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { + if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { dcl &= ~DCL_DimmEccEn; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); @@ -1102,8 +1101,7 @@ static void order_dimms(const struct mem_controller *ctrl) { unsigned long tom_k, base_k; - if ((!CONFIG_HAVE_OPTION_TABLE) || - read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { + if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { tom_k = interleave_chip_selects(ctrl); } else { printk(BIOS_DEBUG, "Interleaving disabled\n"); @@ -1406,7 +1404,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; bios_cycle_time = min_cycle_times[ read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)]; - if (CONFIG_HAVE_OPTION_TABLE && bios_cycle_time > min_cycle_time) { + if (bios_cycle_time > min_cycle_time) { min_cycle_time = bios_cycle_time; } min_latency = 2; diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 1922fab4b6..b05a553c5a 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -19,6 +19,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <pc80/mc146818rtc.h> #include <spd.h> #include "raminit.h" #include "i945.h" @@ -2671,7 +2672,7 @@ static void sdram_save_receive_enable(void) values[3] |= (reg32 >> (24 - 4)) & 0xf0; /* coreboot only uses bytes 0 - 127 for its CMOS values so far - * so we grad bytes 128 - 131 to save the receive enable values + * so we grab bytes 128 - 131 to save the receive enable values */ for (i=0; i<4; i++) |