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| author | Siyuan Wang <wangsiyuanbuaa@gmail.com> | 2013-06-04 19:56:22 +0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-06-04 17:48:47 +0200 |
| commit | 29840e234cf6a58313d7d8bc1db1b2fcd5a33bb1 (patch) | |
| tree | 86ba2db6090c070b74bf7a68ba9cfd2f198f19be /src/northbridge | |
| parent | 5b0420a87b913d7c672fa8cd7b21218b6de3a247 (diff) | |
| download | coreboot-29840e234cf6a58313d7d8bc1db1b2fcd5a33bb1.tar.xz | |
AMD Fam 15tn: Use all memory on systems with more than 4 GB
Take a Parmer board with 4G memory as an example.
Use 'cat /proc/meminfo' to check memory, it reads 'MemTotal 3327540kB'.
Parmer uses 512M as video memory when it has 4G.
3327540+512*1024 = 3851828(kB), so some memory is lost.
When Parmer has 4G memory, TOM2 low is 0x1F000000, TOM2 high is
0x00000001. But in e820 table or coreboot table, the last item is
6: 0000000100000000 - 0000000118000000 = 1 RAM
This is not correct, it should be
6: 0000000100000000 - 000000011f000000 = 1 RAM
This patch changes the memory layout when TOM2 is set.
Change-Id: I4e2d163ae8fe1e65ddc384b520a5112ca067b1d1
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3366
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/agesa/family15tn/northbridge.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index dc68f77e94..f91f69098b 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -811,8 +811,9 @@ static void domain_set_resources(device_t dev) sizek = 0; } else { + uint64_t topmem2 = bsp_topmem2(); basek = 4*1024*1024; - sizek -= (4*1024*1024 - mmio_basek); + sizek = topmem2/1024 - basek; } } |