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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-01-22 15:47:26 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-18 09:15:08 +0000 |
| commit | 3449fafec3123e4bdf117c79e15dfd74bc695e27 (patch) | |
| tree | c96eae868632bba5085ed608444cefd2af0dc5e9 /src/northbridge | |
| parent | 19a37d642050dea6249cc76f752095bc72c4df40 (diff) | |
| download | coreboot-3449fafec3123e4bdf117c79e15dfd74bc695e27.tar.xz | |
nb/intel/i945: Remove 2nd write on SLOTCAP (R/WO)
SLOTCAP is R/WO, it becomes RO after the first write.
Write already done on line #583.
Tested using kprint before and after on 945G-M4 board.
Change-Id: I27579bc634e357490defabb041457aaa010fb1c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 7ab252585a..e8cacf622f 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -552,8 +552,6 @@ static void i945_setup_pci_express_x16(void) u32 reg32; u16 reg16; - u8 reg8; - printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); @@ -733,9 +731,6 @@ static void i945_setup_pci_express_x16(void) reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x328); pci_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); - reg8 = pci_read_config8(PCI_DEV(0, 0x01, 0), SLOTCAP); - pci_write_config8(PCI_DEV(0, 0x01, 0), SLOTCAP, reg8); - /* Additional PCIe graphics setup */ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); reg32 |= (3 << 26); |