diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-30 18:30:21 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-09 23:09:16 +0100 |
| commit | 5db945062c3dc083383f1ed1d1c711ae63ad338f (patch) | |
| tree | ab54c7960ead51b399f6314afbe97b0ceb6a2aeb /src/northbridge | |
| parent | 40d7a454a2ebc7d6a69c51cdd5be7924ea0d0191 (diff) | |
| download | coreboot-5db945062c3dc083383f1ed1d1c711ae63ad338f.tar.xz | |
nb/intel/i945/early_init.c: Add DDR2-667 detection for 945GC
945G-M4 returns : "unknown max. RAM clock (2)",
however, it supports up to DDR2-667MHz.
i945/raminit.c sdram_capabilities_max_supported_memory_frequency()
function returns 667 for case 2.
Change-Id: I3d54c88af897a71db757d00288f3968ed2c19151
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17191
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 5d1a0c28c3..8c41cb8368 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -130,6 +130,7 @@ static void i945_detect_chipset(void) reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); switch (reg8) { case 0: + case 2: printk(BIOS_DEBUG, "up to DDR2-667"); break; case 3: |