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| author | Stefan Reinauer <reinauer@chromium.org> | 2012-05-10 12:15:18 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-05-11 00:30:03 +0200 |
| commit | bb11e60cb2f40da2a5a59dfacda4d46119ddda24 (patch) | |
| tree | f82bbd5b7af6cdae0b77e335db061f870900174f /src/northbridge | |
| parent | 1244f4b52fe423eeac2621672aa1786232f2ca0b (diff) | |
| download | coreboot-bb11e60cb2f40da2a5a59dfacda4d46119ddda24.tar.xz | |
Hook up MRC cache update
Requirements:
- must be in ramstage (locking flash while executing code from there
might not work)
- must be after cbmem is reinitialized (so the mrc cache copy of the
current run can be found)
Change-Id: I8028fb073349ce2b027ef5f8397dc1a1b8b31c02
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1002
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7d7153e73c..6419f8ce17 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -33,6 +33,7 @@ #include <bitops.h> #include <cpu/cpu.h> #include <boot/tables.h> +#include <cbmem.h> #include "chip.h" #include "sandybridge.h" @@ -77,7 +78,6 @@ int add_northbridge_resources(struct lb_memory *mem) return 0; } -void cbmem_post_handling(void); void cbmem_post_handling(void) { update_mrc_cache(); @@ -149,10 +149,6 @@ static void add_fixed_resources(struct device *dev, int index) } } -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif - static void pci_domain_set_resources(device_t dev) { uint64_t tom, me_base, touud; |