I am so stupid to mix up logical and bitwise NOT.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 24 insertions, 25 deletions

diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index ebe558e885..e0b5d0e75e 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -21,60 +21,62 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	print_debug("sdram_enable step 1\r\n");
 	msr = rdmsr(0x20000018);
 	msr.hi = 0x10076013;
-	msr.lo = 0x00004800;
+	msr.lo = 0x00003000;
 	wrmsr(0x20000018, msr);
 
 	msr = rdmsr(0x20000019);
 	msr.hi = 0x18000108;
-	msr.lo = 0x286332a3;
+	msr.lo = 0x696332a3;
 	wrmsr(0x20000019, msr);
 
-	/* 2. release from PMode */
+	/* 2. clock gating for PMode */
 	msr = rdmsr(0x20002004);
-	msr.lo &= !0x04;
-	msr.lo |= 0x03;
+	msr.lo &= ~0x04;
+	msr.lo |=  0x01;
 	wrmsr(0x20002004, msr);
 	/* undocmented bits in GX, in LX there are
 	 * 8 bits in PM1_UP_DLY */
 	msr = rdmsr(0x2000001a);
-	//msr.lo |= 0xF000;
 	msr.lo = 0x0101;
 	wrmsr(0x2000001a, msr);
 	print_debug("sdram_enable step 2\r\n");
 
 	/* 3. release CKE mask to enable CKE */
 	msr = rdmsr(0x2000001d);
-	msr.lo &= !(0x03 << 8);
+	msr.lo &= ~(0x03 << 8);
 	wrmsr(0x2000201d, msr);
 	print_debug("sdram_enable step 3\r\n");
 
-	/* 4. set and clear REF_TST 16 times, more shouldn't hurt */
+	/* 4. set and clear REF_TST 16 times, more shouldn't hurt
+	 * why this is before EMRS and MRS ? */
 	for (i = 0; i < 19; i++) {
 		msr = rdmsr(0x20000018);
 		msr.lo |=  (0x01 << 3);
 		wrmsr(0x20000018, msr);
-		msr.lo &= !(0x01 << 3);
+		msr.lo &= ~(0x01 << 3);
 		wrmsr(0x20000018, msr);
 	}
 	print_debug("sdram_enable step 4\r\n");
 
 	/* 5. set refresh interval */
 	msr = rdmsr(0x20000018);
-	msr.lo |= (0x48 << 8);
+	msr.lo &= ~(0xffff << 8);
+	msr.lo |=  (0x34 << 8);
 	wrmsr(0x20000018, msr);
-
 	/* set refresh staggering to 4 SDRAM clocks */
 	msr = rdmsr(0x20000018);
-	msr.lo &= !(0x03 << 6);
+	msr.lo &= ~(0x03 << 6);
+	msr.lo |=  (0x00 << 6);
 	wrmsr(0x20000018, msr);
+	print_debug("sdram_enable step 5\r\n");
 
-	/* 6. enable RLL, load Extended Mode Register by set and clear PROG_DRAM */
+	/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
 	msr = rdmsr(0x20000018);
 	msr.lo |=  ((0x01 << 28) | 0x01);
 	wrmsr(0x20000018, msr);
-	msr.lo &= !((0x01 << 28) | 0x01);
+	msr.lo &= ~((0x01 << 28) | 0x01);
 	wrmsr(0x20000018, msr);
-	print_debug("sdram_enable step 7\r\n");
+	print_debug("sdram_enable step 6\r\n");
 
 	/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
 	 * it is documented in LX datasheet  */	
@@ -82,19 +84,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	msr = rdmsr(0x20000018);
 	msr.lo |=  ((0x01 << 27) | 0x01);
 	wrmsr(0x20000018, msr);
-	msr.lo &= !((0x01 << 27) | 0x01);
+	msr.lo &= ~((0x01 << 27) | 0x01);
 	wrmsr(0x20000018, msr);
-	print_debug("sdram_enable step 9\r\n");
-
+	print_debug("sdram_enable step 7\r\n");
 
 	/* 8. load Mode Register by set and clear PROG_DRAM */
 	msr = rdmsr(0x20000018);
 	msr.lo |=  0x01;
 	wrmsr(0x20000018, msr);
-	msr.lo &= !0x01;
+	msr.lo &= ~0x01;
 	wrmsr(0x20000018, msr);
-	print_debug("sdram_enable step 10\r\n");
-
+	print_debug("sdram_enable step 8\r\n");
 
 	/* wait 200 SDCLKs */
 	for (i = 0; i < 200; i++)
@@ -102,15 +102,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	/* load RDSYNC */
 	msr = rdmsr(0x2000001f);
-	msr.hi = 0x000ff310;
+	msr.hi = 0x000ff300;
 	msr.lo = 0x00000000;
 	wrmsr(0x2000001f, msr);
-	print_debug("sdram_enable step 10\r\n");
 
 	/* set delay control */
 	msr = rdmsr(0x4c00000f);
-	msr.hi = 0x830d415f;
-	msr.lo = 0x8ea0ad6f;
+	msr.hi = 0x830d415a;
+	msr.lo = 0x8ea0ad6a;
 	wrmsr(0x4c00000f, msr);
 
 	/* DRAM working now?? */