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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-01 11:21:53 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-04 00:53:06 +0200 |
| commit | fbdb085549b6c500e12dc2fb21143a197b4be042 (patch) | |
| tree | 88065a88e408c2b6694d7de039bb57fc7afddddb /src/northbridge | |
| parent | 15c4ab7adf594e0707cdedded8fe6797b17da56a (diff) | |
| download | coreboot-fbdb085549b6c500e12dc2fb21143a197b4be042.tar.xz | |
intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on all boards
with SandyBridge and IvyBridge. To enable MMIO style access,
add explicit PCI IO config write in the bootblock.
Change-Id: I8f957a80bf57df000897c5a080dd5ff131b1ec0d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3576
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/Kconfig | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/bootblock.c | 26 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 2 |
3 files changed, 34 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 3a65782e92..59b618729b 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -20,11 +20,15 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE bool select CACHE_MRC_BIN + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_206AX config NORTHBRIDGE_INTEL_IVYBRIDGE bool select CACHE_MRC_BIN + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_306AX if NORTHBRIDGE_INTEL_SANDYBRIDGE @@ -103,6 +107,10 @@ endif if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/sandybridge/bootblock.c" + config DCACHE_RAM_MRC_VAR_SIZE hex default 0x4000 diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c new file mode 100644 index 0000000000..1c1d49214b --- /dev/null +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -0,0 +1,26 @@ +#include <arch/io.h> + +/* Just re-define this instead of including sandybridge.h. It blows up romcc. */ +#define PCIEXBAR 0x60 + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = 0; + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg); + reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); +} diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index c2d4909f06..583385b3c1 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -49,8 +49,6 @@ static void sandybridge_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32); |