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authorEric Biederman <ebiederm@xmission.com>2003-04-22 19:02:15 +0000
committerEric Biederman <ebiederm@xmission.com>2003-04-22 19:02:15 +0000
commit8ca8d7665d671e10d72b8fcb4d69121d75f7906e (patch)
treedaad2699b4e6b6014bce5a76e82dd9c974801777 /src/pc80
parentb138ac83b53da9abf3dc9a87a1cd4b3d3a8150bd (diff)
downloadcoreboot-8ca8d7665d671e10d72b8fcb4d69121d75f7906e.tar.xz
- Initial checkin of the freebios2 tree
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/pc80')
-rw-r--r--src/pc80/mc146818rtc.c249
-rw-r--r--src/pc80/serial.c93
-rw-r--r--src/pc80/serial.inc106
3 files changed, 448 insertions, 0 deletions
diff --git a/src/pc80/mc146818rtc.c b/src/pc80/mc146818rtc.c
new file mode 100644
index 0000000000..b77653c52e
--- /dev/null
+++ b/src/pc80/mc146818rtc.c
@@ -0,0 +1,249 @@
+#include <console/console.h>
+#include <arch/io.h>
+#include <pc80/mc146818rtc.h>
+#include <boot/linuxbios_tables.h>
+#include <string.h>
+
+#define CMOS_READ(addr) ({ \
+outb((addr),RTC_PORT(0)); \
+inb(RTC_PORT(1)); \
+})
+
+#define CMOS_WRITE(val, addr) ({ \
+outb((addr),RTC_PORT(0)); \
+outb((val),RTC_PORT(1)); \
+})
+
+/* control registers - Moto names
+ */
+#define RTC_REG_A 10
+#define RTC_REG_B 11
+#define RTC_REG_C 12
+#define RTC_REG_D 13
+
+
+/**********************************************************************
+ * register details
+ **********************************************************************/
+#define RTC_FREQ_SELECT RTC_REG_A
+
+/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus,
+ * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
+ * totalling to a max high interval of 2.228 ms.
+ */
+# define RTC_UIP 0x80
+# define RTC_DIV_CTL 0x70
+ /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
+# define RTC_REF_CLCK_4MHZ 0x00
+# define RTC_REF_CLCK_1MHZ 0x10
+# define RTC_REF_CLCK_32KHZ 0x20
+ /* 2 values for divider stage reset, others for "testing purposes only" */
+# define RTC_DIV_RESET1 0x60
+# define RTC_DIV_RESET2 0x70
+ /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
+# define RTC_RATE_SELECT 0x0F
+# define RTC_RATE_NONE 0x00
+# define RTC_RATE_32786HZ 0x01
+# define RTC_RATE_16384HZ 0x02
+# define RTC_RATE_8192HZ 0x03
+# define RTC_RATE_4096HZ 0x04
+# define RTC_RATE_2048HZ 0x05
+# define RTC_RATE_1024HZ 0x06
+# define RTC_RATE_512HZ 0x07
+# define RTC_RATE_256HZ 0x08
+# define RTC_RATE_128HZ 0x09
+# define RTC_RATE_64HZ 0x0a
+# define RTC_RATE_32HZ 0x0b
+# define RTC_RATE_16HZ 0x0c
+# define RTC_RATE_8HZ 0x0d
+# define RTC_RATE_4HZ 0x0e
+# define RTC_RATE_2HZ 0x0f
+
+/**********************************************************************/
+#define RTC_CONTROL RTC_REG_B
+# define RTC_SET 0x80 /* disable updates for clock setting */
+# define RTC_PIE 0x40 /* periodic interrupt enable */
+# define RTC_AIE 0x20 /* alarm interrupt enable */
+# define RTC_UIE 0x10 /* update-finished interrupt enable */
+# define RTC_SQWE 0x08 /* enable square-wave output */
+# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
+# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
+# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
+
+/**********************************************************************/
+#define RTC_INTR_FLAGS RTC_REG_C
+/* caution - cleared by read */
+# define RTC_IRQF 0x80 /* any of the following 3 is active */
+# define RTC_PF 0x40
+# define RTC_AF 0x20
+# define RTC_UF 0x10
+
+/**********************************************************************/
+#define RTC_VALID RTC_REG_D
+# define RTC_VRT 0x80 /* valid RAM and time */
+/**********************************************************************/
+
+
+
+static int rtc_checksum_valid(int range_start, int range_end, int cks_loc)
+{
+ int i;
+ unsigned sum, old_sum;
+ sum = 0;
+ for(i = range_start; i <= range_end; i++) {
+ sum += CMOS_READ(i);
+ }
+ sum = (~sum)&0x0ffff;
+ old_sum = ((CMOS_READ(cks_loc)<<8) | CMOS_READ(cks_loc+1))&0x0ffff;
+ return sum == old_sum;
+}
+
+static void rtc_set_checksum(int range_start, int range_end, int cks_loc)
+{
+ int i;
+ unsigned sum;
+ sum = 0;
+ for(i = range_start; i <= range_end; i++) {
+ sum += CMOS_READ(i);
+ }
+ sum = ~(sum & 0x0ffff);
+ CMOS_WRITE(((sum >> 8) & 0x0ff), cks_loc);
+ CMOS_WRITE(((sum >> 0) & 0x0ff), cks_loc+1);
+}
+
+#define RTC_CONTROL_DEFAULT (RTC_24H)
+#define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ)
+
+#if 0 /* alpha setup */
+#undef RTC_CONTROL_DEFAULT
+#undef RTC_FREQ_SELECT_DEFAULT
+#define RTC_CONTROL_DEFAULT (RTC_SQWE | RTC_24H)
+#define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ)
+#endif
+void rtc_init(int invalid)
+{
+ unsigned char x;
+ int cmos_invalid, checksum_invalid;
+
+ printk_debug("RTC Init\n");
+ /* See if there has been a CMOS power problem. */
+ x = CMOS_READ(RTC_VALID);
+ cmos_invalid = !(x & RTC_VRT);
+
+ /* See if there is a CMOS checksum error */
+ checksum_invalid = !rtc_checksum_valid(PC_CKS_RANGE_START,
+ PC_CKS_RANGE_END,PC_CKS_LOC);
+
+ if (invalid || cmos_invalid || checksum_invalid) {
+ int i;
+ printk_warning("RTC:%s%s%s zeroing cmos\n",
+ invalid?" Clear requested":"",
+ cmos_invalid?" Power Problem":"",
+ checksum_invalid?" Checksum invalid":"");
+#if 0
+ CMOS_WRITE(0, 0x01);
+ CMOS_WRITE(0, 0x03);
+ CMOS_WRITE(0, 0x05);
+ for(i = 10; i < 48; i++) {
+ CMOS_WRITE(0, i);
+ }
+
+ if (cmos_invalid) {
+ /* Now setup a default date of Sat 1 January 2000 */
+ CMOS_WRITE(0, 0x00); /* seconds */
+ CMOS_WRITE(0, 0x02); /* minutes */
+ CMOS_WRITE(1, 0x04); /* hours */
+ CMOS_WRITE(7, 0x06); /* day of week */
+ CMOS_WRITE(1, 0x07); /* day of month */
+ CMOS_WRITE(1, 0x08); /* month */
+ CMOS_WRITE(0, 0x09); /* year */
+ }
+#endif
+ }
+ /* See if there is a LB CMOS checksum error */
+ checksum_invalid = !rtc_checksum_valid(LB_CKS_RANGE_START,
+ LB_CKS_RANGE_END,LB_CKS_LOC);
+ if(checksum_invalid)
+ printk_debug("Invalid CMOS LB checksum\n");
+
+ /* Setup the real time clock */
+ CMOS_WRITE(RTC_CONTROL_DEFAULT, RTC_CONTROL);
+ /* Setup the frequency it operates at */
+ CMOS_WRITE(RTC_FREQ_SELECT_DEFAULT, RTC_FREQ_SELECT);
+ /* Make certain we have a valid checksum */
+ rtc_set_checksum(PC_CKS_RANGE_START,
+ PC_CKS_RANGE_END,PC_CKS_LOC);
+ /* Clear any pending interrupts */
+ (void) CMOS_READ(RTC_INTR_FLAGS);
+}
+
+
+#if USE_OPTION_TABLE == 1
+/* This routine returns the value of the requested bits
+ input bit = bit count from the beginning of the cmos image
+ length = number of bits to include in the value
+ ret = a character pointer to where the value is to be returned
+ output the value placed in ret
+ returns 0 = successful, -1 = an error occurred
+*/
+static int get_cmos_value(unsigned long bit, unsigned long length, void *vret)
+{
+ unsigned char *ret;
+ unsigned long byte,byte_bit;
+ unsigned long i;
+ unsigned char uchar;
+
+ /* The table is checked when it is built to ensure all
+ values are valid. */
+ ret = vret;
+ byte=bit/8; /* find the byte where the data starts */
+ byte_bit=bit%8; /* find the bit in the byte where the data starts */
+ if(length<9) { /* one byte or less */
+ uchar = CMOS_READ(byte); /* load the byte */
+ uchar >>= byte_bit; /* shift the bits to byte align */
+ /* clear unspecified bits */
+ ret[0] = uchar & ((1 << length) -1);
+ }
+ else { /* more that one byte so transfer the whole bytes */
+ for(i=0;length;i++,length-=8,byte++) {
+ /* load the byte */
+ ret[i]=CMOS_READ(byte);
+ }
+ }
+ return 0;
+}
+
+int get_option(void *dest, char *name)
+{
+ extern struct cmos_option_table option_table;
+ struct cmos_option_table *ct;
+ struct cmos_entries *ce;
+ size_t namelen;
+ int found=0;
+
+ /* Figure out how long name is */
+ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH);
+
+ /* find the requested entry record */
+ ct=&option_table;
+ ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length);
+ for(;ce->tag==LB_TAG_OPTION;
+ ce=(struct cmos_entries*)((unsigned char *)ce + ce->size)) {
+ if (memcmp(ce->name, name, namelen) == 0) {
+ found=1;
+ break;
+ }
+ }
+ if(!found) {
+ printk_err("ERROR: No cmos option '%s'\n", name);
+ return(-2);
+ }
+
+ if(get_cmos_value(ce->bit, ce->length, dest))
+ return(-3);
+ if(!rtc_checksum_valid(LB_CKS_RANGE_START,
+ LB_CKS_RANGE_END,LB_CKS_LOC))
+ return(-4);
+ return(0);
+}
+#endif /* USE_OPTION_TABLE */
diff --git a/src/pc80/serial.c b/src/pc80/serial.c
new file mode 100644
index 0000000000..b10d22dcba
--- /dev/null
+++ b/src/pc80/serial.c
@@ -0,0 +1,93 @@
+#include <part/fallback_boot.h>
+
+/* Base Address */
+#ifndef TTYS0_BASE
+#define TTYS0_BASE 0x3f8
+#endif
+
+#ifndef TTYS0_BAUD
+#define TTYS0_BAUD 115200
+#endif
+
+#if ((115200%TTYS0_BAUD) != 0)
+#error Bad ttys0 baud rate
+#endif
+
+#define TTYS0_DIV (115200/TTYS0_BAUD)
+
+/* Line Control Settings */
+#ifndef TTYS0_LCS
+/* Set 8bit, 1 stop bit, no parity */
+#define TTYS0_LCS 0x3
+#endif
+
+#define UART_LCS TTYS0_LCS
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+static int uart_can_tx_byte(void)
+{
+ return inb(TTYS0_BASE + UART_LSR) & 0x20;
+}
+
+static void uart_wait_to_tx_byte(void)
+{
+ while(!uart_can_tx_byte())
+ ;
+}
+
+static void uart_wait_until_sent(void)
+{
+ while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
+ ;
+}
+
+static void uart_tx_byte(unsigned char data)
+{
+ uart_wait_to_tx_byte();
+ outb(data, TTYS0_BASE + UART_TBR);
+ /* Make certain the data clears the fifos */
+ uart_wait_until_sent();
+}
+
+static void uart_init(void)
+{
+ /* disable interrupts */
+ outb(0x0, TTYS0_BASE + UART_IER);
+ /* enable fifo's */
+ outb(0x01, TTYS0_BASE + UART_FCR);
+ /* Set Baud Rate Divisor to 12 ==> 115200 Baud */
+ outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
+#if 0 && USE_OPTION_TABLE == 1
+ {
+ static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 };
+ unsigned ttys0_div, ttys0_index;
+ outb(RTC_BOOT_BYTE + 1, 0x70);
+ ttys0_index = inb(0x71);
+ ttys0_index &= 7;
+ ttys0_div = divisor[ttys0_index];
+ outb(ttys0_div & 0xff, TTYS0_BASE + UART_DLL);
+ outb(0, TTYS0_BASE + UART_DLM);
+ }
+#else
+ outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL);
+ outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM);
+#endif
+ outb(UART_LCS, TTYS0_BASE + UART_LCR);
+}
diff --git a/src/pc80/serial.inc b/src/pc80/serial.inc
new file mode 100644
index 0000000000..b0f12699e1
--- /dev/null
+++ b/src/pc80/serial.inc
@@ -0,0 +1,106 @@
+#include <part/fallback_boot.h>
+
+
+/* Base Address */
+#ifndef TTYS0_BASE
+#define TTYS0_BASE 0x3f8
+#endif
+
+/* Baud Rate */
+#ifndef TTYS0_BAUD
+#define TTYS0_BAUD 115200
+#endif
+
+#if ((115200%TTYS0_BAUD) != 0)
+#error Bad ttys0 baud rate
+#endif
+
+/* Baud Rate Divisor */
+#define TTYS0_DIV (115200/TTYS0_BAUD)
+#define TTYS0_DIV_LO (TTYS0_DIV&0xFF)
+#define TTYS0_DIV_HI ((TTYS0_DIV >> 8)&0xFF)
+
+/* Line Control Settings */
+#ifndef TTYS0_LCS
+/* Set 8bit, 1 stop bit, no parity */
+#define TTYS0_LCS 0x3
+#endif
+
+/* Data */
+#define TTYS0_RBR (TTYS0_BASE+0x00)
+
+/* Control */
+#define TTYS0_TBR TTYS0_RBR
+#define TTYS0_IER (TTYS0_BASE+0x01)
+#define TTYS0_IIR (TTYS0_BASE+0x02)
+#define TTYS0_FCR TTYS0_IIR
+#define TTYS0_LCR (TTYS0_BASE+0x03)
+#define TTYS0_MCR (TTYS0_BASE+0x04)
+#define TTYS0_DLL TTYS0_RBR
+#define TTYS0_DLM TTYS0_IER
+
+/* Status */
+#define TTYS0_LSR (TTYS0_BASE+0x05)
+#define TTYS0_MSR (TTYS0_BASE+0x06)
+#define TTYS0_SCR (TTYS0_BASE+0x07)
+
+#if USE_OPTION_TABLE == 1
+.section ".rom.data"
+ .type div,@object
+ .size div,8
+div:
+.byte 1,2,3,6,12,24,48,96
+
+.previous
+#endif
+
+ jmp serial0
+
+ /* uses: ax, dx */
+#define TTYS0_TX_AL \
+ mov %al, %ah ; \
+9: mov $TTYS0_LSR, %dx ; \
+ inb %dx, %al ; \
+ test $0x20, %al ; \
+ je 9b ; \
+ mov $TTYS0_TBR, %dx ; \
+ mov %ah, %al ; \
+ outb %al, %dx
+
+
+serial0:
+ /* Set 115.2Kbps,8n1 */
+ /* Set 8bit, 1 stop bit, no parity, DLAB */
+ mov $TTYS0_LCR, %dx
+ mov $(TTYS0_LCS | 0x80), %al
+ out %al, %dx
+
+ /* set Baud Rate Divisor to 1 ==> 115200 Buad */
+#if USE_OPTION_TABLE == 1
+
+ movb $(RTC_BOOT_BYTE+1), %al
+ outb %al, $0x70
+ xorl %edx,%edx
+ inb $0x71, %al
+ andb $7,%al
+ movb %al,%dl
+ movb div(%edx),%al
+ mov $TTYS0_DLL, %dx
+ out %al, %dx
+ mov $TTYS0_DLM, %dx
+ xorb %al,%al
+ out %al, %dx
+#else
+ mov $TTYS0_DLL, %dx
+ mov $TTYS0_DIV_LO, %al
+ out %al, %dx
+ mov $TTYS0_DLM, %dx
+ mov $TTYS0_DIV_HI, %al
+ out %al, %dx
+#endif
+ /* Disable DLAB */
+ mov $TTYS0_LCR, %dx
+ mov $(TTYS0_LCS & 0x7f), %al
+ out %al, %dx
+
+