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| author | Myles Watson <mylesgw@gmail.com> | 2010-03-19 02:33:40 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2010-03-19 02:33:40 +0000 |
| commit | 342619526c0e7bd084c6739782e4b332e01fa564 (patch) | |
| tree | 84a934c096bf9e89e4e76e52d66ff32db049a76c /src/pc80 | |
| parent | 78acf932912669eb0eb7f7280da1b3c550035ebb (diff) | |
| download | coreboot-342619526c0e7bd084c6739782e4b332e01fa564.tar.xz | |
Get rid of a few warnings:
1. Add some more prototypes to lib.h
2. Include console.h when not using romcc
3. Eliminate an unused function
4. Set a default for SSE2, since it is just for ramtest performance
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/pc80')
| -rw-r--r-- | src/pc80/serial.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/pc80/serial.c b/src/pc80/serial.c index cddce333b3..837d112338 100644 --- a/src/pc80/serial.c +++ b/src/pc80/serial.c @@ -1,3 +1,5 @@ +#include <lib.h> /* Prototypes */ + /* Base Address */ #ifndef CONFIG_TTYS0_BASE #define CONFIG_TTYS0_BASE 0x3f8 |