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| author | Ed Swierk <eswierk@arastra.com> | 2008-03-30 11:31:15 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2008-03-30 11:31:15 +0000 |
| commit | 71f846c13769f037fbdf649224d03377948b7fa9 (patch) | |
| tree | 8fb04b3d55db914af98a7f35e89f6b5af1799679 /src/ram | |
| parent | 1e185e8561bc42b0f77159e4fa7ef0c652a2f6eb (diff) | |
| download | coreboot-71f846c13769f037fbdf649224d03377948b7fa9.tar.xz | |
Like other Intel chipsets, the Intel 3100 has a TCO timer that reboots
the system automatically unless software resets the timer
periodically. The extra reboot extends boot time by several seconds.
The attached patch adds a function to the Intel 3100 southbridge code
that halts the TCO timer, thus preventing this extra reboot, and calls
the function early in the boot process on the Mt. Arvon board.
It also fixes a bug in the LPC device initialization -- the ACPI BAR
enable flag is bit 7, not bit 4.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/ram')
0 files changed, 0 insertions, 0 deletions