diff options
author | Eric Biederman <ebiederm@xmission.com> | 2003-04-22 19:02:15 +0000 |
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committer | Eric Biederman <ebiederm@xmission.com> | 2003-04-22 19:02:15 +0000 |
commit | 8ca8d7665d671e10d72b8fcb4d69121d75f7906e (patch) | |
tree | daad2699b4e6b6014bce5a76e82dd9c974801777 /src/sdram | |
parent | b138ac83b53da9abf3dc9a87a1cd4b3d3a8150bd (diff) | |
download | coreboot-8ca8d7665d671e10d72b8fcb4d69121d75f7906e.tar.xz |
- Initial checkin of the freebios2 tree
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/sdram')
-rw-r--r-- | src/sdram/generic_dump_spd.c | 25 | ||||
-rw-r--r-- | src/sdram/generic_sdram.c | 35 |
2 files changed, 60 insertions, 0 deletions
diff --git a/src/sdram/generic_dump_spd.c b/src/sdram/generic_dump_spd.c new file mode 100644 index 0000000000..27f1844d3c --- /dev/null +++ b/src/sdram/generic_dump_spd.c @@ -0,0 +1,25 @@ +void dump_spd_registers(void) +{ + unsigned device; + device = SMBUS_MEM_DEVICE_START; + printk_debug("\n"); + while(device <= SMBUS_MEM_DEVICE_END) { + int status = 0; + int i; + printk_debug("dimm %02x", device); + for(i = 0; (i < 256) && (status == 0); i++) { + unsigned char byte; + if ((i % 20) == 0) { + printk_debug("\n%3d: ", i); + } + status = smbus_read_byte(device, i, &byte); + if (status != 0) { + printk_debug("bad device\n"); + continue; + } + printk_debug("%02x ", byte); + } + device += SMBUS_MEM_DEVICE_INC; + printk_debug("\n"); + } +} diff --git a/src/sdram/generic_sdram.c b/src/sdram/generic_sdram.c new file mode 100644 index 0000000000..be5ae87407 --- /dev/null +++ b/src/sdram/generic_sdram.c @@ -0,0 +1,35 @@ +void sdram_no_memory(void) +{ + print_err("No memory!!\r\n"); + while(1) { + hlt(); + } +} + +/* Setup SDRAM */ +void sdram_initialize(void) +{ + print_debug("Ram1\r\n"); + /* Set the registers we can set once to reasonable values */ + sdram_set_registers(); + + print_debug("Ram2\r\n"); + /* Now setup those things we can auto detect */ + sdram_set_spd_registers(); + + print_debug("Ram3\r\n"); + /* Now that everything is setup enable the SDRAM. + * Some chipsets do the work for use while on others + * we need to it by hand. + */ + sdram_enable(); + + print_debug("Ram4\r\n"); + sdram_first_normal_reference(); + + print_debug("Ram5\r\n"); + sdram_enable_refresh(); + sdram_special_finishup(); + + print_debug("Ram6\r\n"); +} |