security/intel/stm: Add STM support

This update is a combination of all four of the patches so that the
commit can be done without breaking parts of coreboot.  This possible
breakage is because of the cross-dependencies between the original
separate patches would cause failure because of data structure changes.

security/intel/stm

This directory contains the functions that check and move the STM to the
MSEG, create its page tables, and create the BIOS resource list.

The STM page tables is a six page region located in the MSEG and are
pointed to by the CR3 Offset field in the MSEG header.  The initial
page tables will identity map all memory between 0-4G.  The STM starts
in IA32e mode, which requires page tables to exist at startup.

The BIOS resource list defines the resources that the SMI Handler is
allowed to access.  This includes the SMM memory area where the SMI
handler resides and other resources such as I/O devices.  The STM uses
the BIOS resource list to restrict the SMI handler's accesses.

The BIOS resource list is currently located in the same area as the
SMI handler.  This location is shown in the comment section before
smm_load_module in smm_module_loader.c

Note: The files within security/intel/stm come directly from their
Tianocore counterparts.  Unnecessary code has been removed and the
remaining code has been converted to meet coreboot coding requirements.

For more information see:
     SMI Transfer Monitor (STM) User Guide, Intel Corp.,
     August 2015, Rev 1.0, can be found at firmware.intel.com

include/cpu/x86:

Addtions to include/cpu/x86 for STM support.

cpu/x86:

STM Set up - The STM needs to be loaded into the MSEG during BIOS
initialization and the SMM Monitor Control MSR be set to indicate
that an STM is in the system.

cpu/x86/smm:

SMI module loader modifications needed to set up the
SMM descriptors used by the STM during its initialization

Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec
Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: ron minnich <rminnich@gmail.com>

1 files changed, 49 insertions, 0 deletions

diff --git a/src/security/intel/stm/Kconfig b/src/security/intel/stm/Kconfig
new file mode 100644
index 0000000000..a74eba8522
--- /dev/null
+++ b/src/security/intel/stm/Kconfig
@@ -0,0 +1,49 @@
+
+
+config STM
+	bool "Enable STM"
+	default n
+	depends on SMM_TSEG
+	select USE_BLOBS
+
+	help
+	  Enabling the STM will load a simple hypervisor into SMM that will
+	  restrict the actions of the SMI handler, which is the part of BIOS
+	  that functions in system management mode (SMM).  The kernel can
+	  configure the STM to prevent the SMI handler from accessing platform
+	  resources.
+	  The STM closes a vulnerability in Intel TXT (D-RTM)
+	  The SMI handler provides a list of platform resources that it
+	  requires access to the STM during STM startup, which the kernel
+	  cannot override.
+	  An additional capability, called STM-PE, provides a protected
+	  execution capability that allows modules to be executed without
+	  observation and interference. Examples of usage include kernel
+	  introspection and virtualized trusted platform module (vTPM).
+	  Requirement: SMM must be enabled and there must be sufficient room
+	  within the TSEG to fit the MSEG.
+
+if STM
+
+menu "SMI Transfer Monitor (STM)"
+
+config MSEG_SIZE
+	hex "mseg size"
+	default 0x400000
+	help
+		STM only - 0x100000
+		STM/PE   - 0x300000+ depending on the amount of memory needed
+		                     for the protected execution virtual
+		                     machine (VM/PE)
+
+config BIOS_RESOURCE_LIST_SIZE
+	hex "bios_resource_list_size"
+	default 0x1000
+
+config STM_BINARY_FILE
+	string "STM binary file"
+	default "3rdparty/blobs/cpu/intel/stm/stm.bin"
+
+endmenu #STM
+
+endif