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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-02-02 19:00:49 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-05-20 16:21:59 +0000 |
| commit | fc6cc717cebabe09f24f4102c2983859f7f0ece7 (patch) | |
| tree | 30b53e3100800ad71db8d990bbc361be676f0e94 /src/security/intel/txt/ramstage.c | |
| parent | c423ce2f7f5a072e04a6cefa0c2c7f154cce5435 (diff) | |
| download | coreboot-fc6cc717cebabe09f24f4102c2983859f7f0ece7.tar.xz | |
security/intel/txt: Add weak function to skip TXT lockdown
RAS error injection requires TXT and other related lockdown steps to
be skipped.
Change-Id: If9193a03be7e1345740ddc705f20dd4d05f3af26
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/security/intel/txt/ramstage.c')
| -rw-r--r-- | src/security/intel/txt/ramstage.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index c830f975a6..85fa931474 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -289,6 +289,11 @@ static void txt_initialize_heap(void) push_sinit_heap(&heap_struct, NULL, 0); } +__weak bool skip_intel_txt_lockdown(void) +{ + return false; +} + /** * Finalize the TXT device. * @@ -300,6 +305,9 @@ static void txt_initialize_heap(void) */ static void lockdown_intel_txt(void *unused) { + if (skip_intel_txt_lockdown()) + return; + const uint64_t status = read64((void *)TXT_SPAD); uint32_t txt_feature_flags = 0; |