diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-16 00:47:45 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-22 20:00:19 +0000 |
| commit | 28d040840998aa616b403fb9325238374d3730b8 (patch) | |
| tree | e131d6bf1588e37936c9b16dc8449a9bbbf4c187 /src/security/intel | |
| parent | 5a6daa6b7288eed6561d90fdb7afebbc01ade869 (diff) | |
| download | coreboot-28d040840998aa616b403fb9325238374d3730b8.tar.xz | |
sec/intel/txt/common.c: Only log ACM error on failure
The TXT_BIOSACM_ERRORCODE register is only valid if TXT_SPAD bit 62 is
set, or if CBnT is supported and bit 61 is set. Moreover, this is only
applicable to LT-SX (i.e. platforms supporting Intel TXT for Servers).
This allows TXT to work on client platforms, where these registers are
regular scratchpads and are not necessarily written to by the BIOS ACM.
Change-Id: If047ad79f12de5e0f34227198ee742b9e2b5eb54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46492
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/security/intel')
| -rw-r--r-- | src/security/intel/txt/common.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 5f8a976946..737ab0a4be 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -303,8 +303,6 @@ int intel_txt_run_bios_acm(const u8 input_params) intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); return -1; } - if (intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)) != 1) - return -1; return 0; } |