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| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-09-08 11:30:46 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-14 07:04:07 +0000 |
| commit | 426e07aaf20ae917dd65997bf46667d56881444a (patch) | |
| tree | 6505ebb00065f7d64593a88e2f74f2ed8cefbe38 /src/security/intel | |
| parent | 033038fd489cb0e37303e765bfb077354714012e (diff) | |
| download | coreboot-426e07aaf20ae917dd65997bf46667d56881444a.tar.xz | |
mb/google/dedede/variants/drawcia: Increase PL2 value from 15W to 20W
Jasper Lake SoC supports PL2 (Power Limit2) as 20W. Increase PL2 value from 15W to 20W.
BRANCH=None
BUG=b:166656373
TEST=Built and tested on drawlat system
Change-Id: I82d6792907bb1c88cc9dd57d1eaeda8421c12fb2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45162
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/security/intel')
0 files changed, 0 insertions, 0 deletions