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| author | Christian Walter <christian.walter@9elements.com> | 2019-07-23 10:26:30 +0200 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2019-08-06 12:07:49 +0000 |
| commit | 0bd84ed25066fc28d3a0750d429a29c64bfb955d (patch) | |
| tree | 7b61020acdf77ec01a1163851713386d3724ac31 /src/security/vboot/Makefile.inc | |
| parent | 6d2dbe11ae1f4ae21b3f15699831e53d47e270cd (diff) | |
| download | coreboot-0bd84ed25066fc28d3a0750d429a29c64bfb955d.tar.xz | |
security/vboot: Add Support for Intel PTT
Add support for Intel PTT. For supporting Intel PTT we need to disable
read and write access to the TPM NVRAM during the bootblock. TPM NVRAM
will only be available once the DRAM is initialized. To circumvent this,
we mock secdata if HAVE_INTEL_PTT is set. The underlying problem is,
that the iTPM only supports a stripped down instruction set while the
Intel ME is not fully booted up. Details can be found in Intel document
number 571993 - Paragraph 2.10.
Change-Id: I08c9a839f53f96506be5fb68f7c1ed5bf6692505
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/security/vboot/Makefile.inc')
| -rw-r--r-- | src/security/vboot/Makefile.inc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 6d195292e2..d554f103d6 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -88,6 +88,11 @@ else verstage-y += secdata_tpm.c romstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += secdata_tpm.c endif + +ifneq ($(CONFIG_TPM1)$(CONFIG_TPM2),) +verstage-y += tpm_common.c +endif + romstage-y += vboot_logic.c romstage-y += common.c |