diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 16:12:29 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-24 13:43:34 +0000 |
| commit | c3e9ba03b6e8f888680b0117df8d6405eebfd01a (patch) | |
| tree | 23d673163b70f03e4aad68640daa09aa96f4999f /src/security | |
| parent | dce3927f208c75ec854f966e99c86a8081aca42d (diff) | |
| download | coreboot-c3e9ba03b6e8f888680b0117df8d6405eebfd01a.tar.xz | |
nb/intel/gm45: Put stage cache in TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Tested on Lenovo thinkpad X200: on cold boot the external stage cache
gets created and the cached ramstage gets successfully used on the S3
resume path.
Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25604
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/security')
0 files changed, 0 insertions, 0 deletions