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authorBenjamin Doron <benjamin.doron00@gmail.com>2020-03-14 01:53:25 +0000
committerNico Huber <nico.h@gmx.de>2020-10-15 00:01:05 +0000
commitadcb870837518283fac6eac24a628d42912fd4a3 (patch)
tree453779d2c48fc8da110e8e633319f1b62ce45ac5 /src/security
parent3e314636a63e5f981eb038a2767bd606fea9f468 (diff)
downloadcoreboot-adcb870837518283fac6eac24a628d42912fd4a3.tar.xz
soc/intel/skylake: Configure L1 substates for PCH root ports
Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration. Tested on an Acer Aspire VN7-572G (Skylake-U). Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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