summaryrefslogtreecommitdiff
path: root/src/security
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-02 09:39:36 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-11-07 14:08:46 +0000
commit32c8de10b03d0f7fccd4e4dc10a20f97e57cc428 (patch)
treeaa9b0f477e30c6cfb30c998721f5d5bc1d14b975 /src/security
parent3042af62562346b2dbcc05f8c614d3380a84d559 (diff)
downloadcoreboot-32c8de10b03d0f7fccd4e4dc10a20f97e57cc428.tar.xz
Rangeley: Fix incorrect BCLK
Not all Rangeley SKUs have a fixed 100MHz BCLK. As per BIOS Writer's Guide, BCLK is available in MSR_FSB_FREQ 0xCD[1:0]. Using fixed BCLK was causing wrong values of core frequencies in _PSS table for SKUs that do not have BCLK=100MHz. Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f Signed-off-by: Hannah Williams <hannah.williams@dell.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35348 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/security')
0 files changed, 0 insertions, 0 deletions