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authorKarthikeyan Ramasubramanian <kramasub@google.com>2021-04-22 16:59:08 -0600
committerPatrick Georgi <pgeorgi@google.com>2021-04-26 08:28:29 +0000
commit5ad85d95cd656996acbfef5c8bea791662b551cd (patch)
treedb3452af1dc4f584c7b1257fe8229dcd13917020 /src/soc/amd/Kconfig
parent250e610fa082473b3592d06c69316ec1daa88116 (diff)
downloadcoreboot-5ad85d95cd656996acbfef5c8bea791662b551cd.tar.xz
soc/amd/cezanne/fsp_m_params: Configure the s0i3_enable UPD
Configure the S0i3 enable UPD based on the mainboard configuration. BUG=b:178728116 TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the sleep state configuration from the mainboard. Change-Id: I18f43e964d1c70317155394257a5e2c1900816bb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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