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| author | Raul E Rangel <rrangel@chromium.org> | 2021-03-24 16:53:37 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-03-29 18:57:28 +0000 |
| commit | 95b3dc3da9b10cb3445fdd789bfdfb0615f16ef4 (patch) | |
| tree | 749f7b336deab304b42540a4bde8c74a2967ac29 /src/soc/amd/cezanne/Kconfig | |
| parent | f4e90e8a611a8ce29e3a990923ccdb99b919c21c (diff) | |
| download | coreboot-95b3dc3da9b10cb3445fdd789bfdfb0615f16ef4.tar.xz | |
soc/amd/cezanne: Implement PROVIDES_ROM_SHARING
BUG=none
TEST=Build guybrush and verified with the PPR that the register and bits
are still the same
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0619f84cf82cbb90ded9dfd58afa6acc9520fb8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/cezanne/Kconfig')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 5e0e1a6d6d..9a108c95fb 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -30,6 +30,7 @@ config SOC_SPECIFIC_OPTIONS select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 + select PROVIDES_ROM_SHARING select RESET_VECTOR_IN_RAM select RTC select SOC_AMD_COMMON @@ -195,6 +196,14 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 150 +config DISABLE_SPI_FLASH_ROM_SHARING + def_bool n + help + Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin + which indicates a board level ROM transaction request. This + removes arbitration with board and assumes the chipset controls + the SPI flash bus entirely. + menu "PSP Configuration Options" config AMD_FWM_POSITION_INDEX |