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authorMathew King <mathewk@chromium.org>2021-03-04 08:26:51 -0700
committerMartin Roth <martinroth@google.com>2021-03-10 23:47:03 +0000
commitc519bff9c15ebefd790f844921b314bcf080bdcc (patch)
treecd771a55ba6d9fe81813e10983b274be07ca1bf3 /src/soc/amd/cezanne/Kconfig
parent807ce6258a731aa3387359660d29b42cc52b46d3 (diff)
downloadcoreboot-c519bff9c15ebefd790f844921b314bcf080bdcc.tar.xz
soc/amd/cezanne: Add USB ports to chipset.cb
BUG=b:180529005 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I16de0869abd1eff4e89cf1b8128775858702acb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/Kconfig')
-rw-r--r--src/soc/amd/cezanne/Kconfig2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 290fc229a6..01b38e06fb 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -15,6 +15,8 @@ config SOC_SPECIFIC_OPTIONS
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
+ select DRIVERS_USB_ACPI
+ select DRIVERS_USB_PCI_XHCI
select FSP_COMPRESS_FSP_M_LZMA
select FSP_COMPRESS_FSP_S_LZMA
select HAVE_ACPI_TABLES