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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-03-11 19:37:32 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-03-12 20:31:55 +0000 |
| commit | e77d939321e79ae04a1ebc8142b9d5949c6fd4d1 (patch) | |
| tree | 180a855e3ffe3d187de5e116194e4c06dda67cef /src/soc/amd/cezanne/Makefile.inc | |
| parent | 8494d8a1653658e05cf86c6c1d50cbb9039c1c52 (diff) | |
| download | coreboot-e77d939321e79ae04a1ebc8142b9d5949c6fd4d1.tar.xz | |
soc/amd/cezanne: add XHCI SCI/GEVENT setup
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32fd9b7165306266613e8497b5d07473b5fea02d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/Makefile.inc')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index aa82c99ba4..f099ad81d8 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -35,6 +35,7 @@ ramstage-y += pcie_gpp.c ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c +ramstage-y += xhci.c smm-y += gpio.c smm-y += smihandler.c |