diff options
author | Zheng Bao <fishbaozi@gmail.com> | 2021-03-16 15:28:49 +0800 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2021-03-22 03:43:25 +0000 |
commit | b0f00ed4268573269c5f2085da1c92566768ece3 (patch) | |
tree | f0b39c870819c39966b9aade0eed4dcc30f515b3 /src/soc/amd/cezanne/Makefile.inc | |
parent | 7a0b9c5e7369dc98e559e821864e324e3881ec49 (diff) | |
download | coreboot-b0f00ed4268573269c5f2085da1c92566768ece3.tar.xz |
soc/amd/cezanne: Get I2C specific code for cezanne
Add macros, settings and callbacks to support I2C for cezanne.
Change-Id: Ic480681d4b7c6fb8591e729090e4faeb5fccf800
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/cezanne/Makefile.inc')
-rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index f099ad81d8..91a16d89ba 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -11,19 +11,23 @@ all-y += aoac.c bootblock-y += bootblock.c bootblock-y += early_fch.c +bootblock-y += i2c.c bootblock-y += gpio.c bootblock-y += reset.c bootblock-y += uart.c +verstage-y += i2c.c verstage_x86-y += gpio.c verstage_x86-y += reset.c verstage_x86-y += uart.c +romstage-y += i2c.c romstage-y += gpio.c romstage-y += reset.c romstage-y += romstage.c romstage-y += uart.c +ramstage-y += i2c.c ramstage-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c |