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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-04-19 21:40:35 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-21 22:13:30 +0000 |
| commit | d3be9ba9023857aaa362e6f2c37766101f7f9d06 (patch) | |
| tree | 1f48acde6ab5352f8a776878b4a77584592057e8 /src/soc/amd/cezanne/chip.h | |
| parent | 5dea8271b6e3394c414e4d00398dfcda800e7da8 (diff) | |
| download | coreboot-d3be9ba9023857aaa362e6f2c37766101f7f9d06.tar.xz | |
soc/amd/cezanne: add SMU settings to devicetree
BUG=b:182297189
TEST=none
Cq-Depend: chrome-internal:3772425
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifbcc85cc10d59f1418bbf0ed4a0dc7549d589a26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/chip.h')
| -rw-r--r-- | src/soc/amd/cezanne/chip.h | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index af78ddfd9a..7753ab8623 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -27,6 +27,45 @@ struct soc_amd_cezanne_config { DOWNCORE_7 = 10, /* Run with 7 physical cores */ } downcore_mode; bool disable_smt; /* disable second thread on all physical cores */ + + uint8_t stt_control; + uint8_t stt_pcb_sensor_count; + uint16_t stt_min_limit; + uint16_t stt_m1; + uint16_t stt_m2; + uint16_t stt_m3; + uint16_t stt_m4; + uint16_t stt_m5; + uint16_t stt_m6; + uint16_t stt_c_apu; + uint16_t stt_c_gpu; + uint16_t stt_c_hs2; + uint16_t stt_alpha_apu; + uint16_t stt_alpha_gpu; + uint16_t stt_alpha_hs2; + uint16_t stt_skin_temp_apu; + uint16_t stt_skin_temp_gpu; + uint16_t stt_skin_temp_hs2; + uint16_t stt_error_coeff; + uint16_t stt_error_rate_coefficient; + + uint8_t stapm_boost; + uint32_t stapm_time_constant; + uint32_t apu_only_sppt_limit; + uint32_t sustained_power_limit; + uint32_t fast_ppt_limit; + uint32_t slow_ppt_limit; + + uint8_t smartshift_enable; + + uint8_t system_configuration; + + uint8_t cppc_ctrl; + uint8_t cppc_perf_limit_max_range; + uint8_t cppc_perf_limit_min_range; + uint8_t cppc_epp_max_range; + uint8_t cppc_epp_min_range; + uint8_t cppc_preferred_cores; }; #endif /* CEZANNE_CHIP_H */ |