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| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2021-05-11 14:20:23 +0800 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2021-05-12 15:40:08 +0000 |
| commit | 7216053a4207bd6aebd7250e94d59de5e6563680 (patch) | |
| tree | 6538cbcf4fce9091b911dc46ab0ead3b353eca20 /src/soc/amd/cezanne/chip.h | |
| parent | f963a0f8e5ac5d68b17bb1f703cab617260a3fa6 (diff) | |
| download | coreboot-7216053a4207bd6aebd7250e94d59de5e6563680.tar.xz | |
mb/google/dedede/var/metaknight: Update DPTF parameters
Remove TSR2 and use DPTF parameters from internal thermal team.
BUG=b:175938681
TEST=build and boot to OS.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If0ec1ec48b8971efe87f1f8d10332a9c16352122
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/soc/amd/cezanne/chip.h')
0 files changed, 0 insertions, 0 deletions