diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2021-05-06 16:08:09 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-05-10 04:14:52 +0000 |
| commit | 3e1943ec46d04aff01c7fc755ac371e33e7a2dcb (patch) | |
| tree | edef0c3bbdba72c95929b0835512b405ba631170 /src/soc/amd/cezanne/fch.c | |
| parent | a204cdf75b65c86f95cc9083e8a003baa3209071 (diff) | |
| download | coreboot-3e1943ec46d04aff01c7fc755ac371e33e7a2dcb.tar.xz | |
soc/amd/cezanne: Force resets to be cold
Cezanne must use cold resets. Change the warm reset request to always
set TOGGLE_ALL_PWR_GOOD. And, since the bit is sticky across power
cycles, set it early for good measure.
BUG=b:184281092
TEST=Majolica successfully resets using 0xcf9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/cezanne/fch.c')
| -rw-r--r-- | src/soc/amd/cezanne/fch.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 028ffec17b..f02d1acec5 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -113,8 +113,14 @@ static void fch_init_acpi_ports(void) PM_ACPI_TIMER_EN_EN); } +static void fch_init_resets(void) +{ + pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); +} + void fch_init(void *chip_info) { + fch_init_resets(); i2c_soc_init(); fch_init_acpi_ports(); |