diff options
| author | Kangheui Won <khwon@chromium.org> | 2021-04-15 17:34:09 +1000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-23 16:34:22 +0000 |
| commit | 62047e582b0eaed085cf452630c1260f092b8782 (patch) | |
| tree | 24bd88769b4e0c5273cfffef2770e09cd09aacdb /src/soc/amd/cezanne/i2c.c | |
| parent | f2996328311f6281218ce5acc8ffa3e232d2667a (diff) | |
| download | coreboot-62047e582b0eaed085cf452630c1260f092b8782.tar.xz | |
soc/amd/cezanne: fix i2c compiler errors on non-x86
if ENV_X86 is not true we had several compile errors in i2c code. Fix
them before we add code for psp_verstage which is non-x86.
BUG=b:182477057
BRANCH=none
TEST=build
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I0796671dd34ab2d0f123c904a88c57cdad116a57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/cezanne/i2c.c')
| -rw-r--r-- | src/soc/amd/cezanne/i2c.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/i2c.c b/src/soc/amd/cezanne/i2c.c index ec6cb0382d..6571ff50bd 100644 --- a/src/soc/amd/cezanne/i2c.c +++ b/src/soc/amd/cezanne/i2c.c @@ -2,6 +2,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/i2c.h> +#include <console/console.h> #include <soc/i2c.h> #include <soc/southbridge.h> #include "chip.h" @@ -14,7 +15,7 @@ static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = { { I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" } }; #else -static struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_CNT] = { +static struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = { { I2C_MASTER_MODE, 0, "" }, { I2C_MASTER_MODE, 0, "" }, { I2C_MASTER_MODE, 0, "" }, |