diff options
| author | Kangheui Won <khwon@chromium.org> | 2021-04-15 17:34:09 +1000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-23 16:34:22 +0000 |
| commit | 62047e582b0eaed085cf452630c1260f092b8782 (patch) | |
| tree | 24bd88769b4e0c5273cfffef2770e09cd09aacdb /src/soc/amd/cezanne/include | |
| parent | f2996328311f6281218ce5acc8ffa3e232d2667a (diff) | |
| download | coreboot-62047e582b0eaed085cf452630c1260f092b8782.tar.xz | |
soc/amd/cezanne: fix i2c compiler errors on non-x86
if ENV_X86 is not true we had several compile errors in i2c code. Fix
them before we add code for psp_verstage which is non-x86.
BUG=b:182477057
BRANCH=none
TEST=build
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I0796671dd34ab2d0f123c904a88c57cdad116a57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/cezanne/include')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/i2c.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/iomap.h | 10 |
2 files changed, 6 insertions, 5 deletions
diff --git a/src/soc/amd/cezanne/include/soc/i2c.h b/src/soc/amd/cezanne/include/soc/i2c.h index d69925dfc3..674c8e37b1 100644 --- a/src/soc/amd/cezanne/include/soc/i2c.h +++ b/src/soc/amd/cezanne/include/soc/i2c.h @@ -22,5 +22,6 @@ #define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx #define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx +void i2c_set_bar(unsigned int bus, uintptr_t bar); #endif /* AMD_CEZANNE_I2C_H */ diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 8f33794acf..83bb8176fa 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -3,6 +3,11 @@ #ifndef AMD_CEZANNE_IOMAP_H #define AMD_CEZANNE_IOMAP_H +#define I2C_MASTER_DEV_COUNT 4 +#define I2C_MASTER_START_INDEX 0 +#define I2C_PERIPHERAL_DEV_COUNT 0 /* TODO: Only master for now. */ +#define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) + #if ENV_X86 /* MMIO Ranges */ @@ -16,11 +21,6 @@ /* FCH AL2AHB Registers */ #define ALINK_AHB_ADDRESS 0xfedc0000 -#define I2C_MASTER_DEV_COUNT 4 -#define I2C_MASTER_START_INDEX 0 -#define I2C_PERIPHERAL_DEV_COUNT 0 /* TODO: Only master for now. */ -#define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) - #define APU_I2C0_BASE 0xfedc2000 #define APU_I2C1_BASE 0xfedc3000 #define APU_I2C2_BASE 0xfedc4000 |