diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-03-31 13:15:07 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-04-05 19:25:26 +0000 |
| commit | 92e66cc4e30f25e580ca25fa1c9a596ff53d83a2 (patch) | |
| tree | e0a2e86584eea22c072abe3c4d47c8a732001d0a /src/soc/amd/cezanne/include | |
| parent | 7a347afa955e6ab3931a7a0db8fee5bb3c04b9d3 (diff) | |
| download | coreboot-92e66cc4e30f25e580ca25fa1c9a596ff53d83a2.tar.xz | |
soc/amd/cezanne: Add soc/msr.h
This is a copy of picasso.
BUG=b:184151560
TEST=Compared with the cezanne PPR.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia4bc40daa971c126c2596837155312d411b91a06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/include')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/msr.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h new file mode 100644 index 0000000000..cc1f77e35b --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/msr.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_MSR_H +#define AMD_CEZANNE_MSR_H + +/* MSRC001_00[6B:64] P-state [7:0] bit definitions */ +#define PSTATE_DEF_HI_ENABLE_SHIFT 31 +#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) +#define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 +#define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) +#define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 +#define PSTATE_DEF_LO_CUR_VAL_MASK (0xFF << PSTATE_DEF_LO_CUR_VAL_SHIFT) +#define PSTATE_DEF_LO_CORE_VID_SHIFT 14 +#define PSTATE_DEF_LO_CORE_VID_MASK (0xFF << PSTATE_DEF_LO_CORE_VID_SHIFT) +#define PSTATE_DEF_LO_FREQ_DIV_SHIFT 8 +#define PSTATE_DEF_LO_FREQ_DIV_MASK (0x3F << PSTATE_DEF_LO_FREQ_DIV_SHIFT) +#define PSTATE_DEF_LO_FREQ_DIV_MIN 0x8 +#define PSTATE_DEF_LO_EIGHTH_STEP_MAX 0x1A +#define PSTATE_DEF_LO_FREQ_DIV_MAX 0x3E +#define PSTATE_DEF_LO_FREQ_MUL_SHIFT 0 +#define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) +#define PSTATE_DEF_LO_CORE_FREQ_BASE 25 + +#endif /* AMD_CEZANNE_MSR_H */ |