diff options
| author | Kangheui Won <khwon@chromium.org> | 2021-04-29 15:19:03 +1000 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-05-02 18:25:16 +0000 |
| commit | b997b0a04e758207a8db9900eb79a3f59c546193 (patch) | |
| tree | fa1f65ef91a6f5bfa7f0e46e267feee159317aab /src/soc/amd/cezanne/include | |
| parent | d8928e438b6bce4af4963eaec8a8e6b29cb32736 (diff) | |
| download | coreboot-b997b0a04e758207a8db9900eb79a3f59c546193.tar.xz | |
soc/amd/cezanne: add verstage files
Add support for psp_verstage compilation.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Iac48c92a787adabfdaec96b6e8d2e24708d7e652
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/cezanne/include')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/psp_verstage_addr.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h new file mode 100644 index 0000000000..bdc46cb84e --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_PSP_VERSTAGE_ADDR_H +#define AMD_CEZANNE_PSP_VERSTAGE_ADDR_H + +/* + * Start of available space is 0x36000 and this is where the + * header for the user app (verstage) must be mapped. + * Size is 0x14000 bytes + */ +#define PSP_SRAM_START 0x36000 +#define PSP_SRAM_SIZE (80K) +#define VERSTAGE_START PSP_SRAM_START + +/* + * The top of the stack must be 4k aligned, so set the bottom as 4k aligned + * and make the size a multiple of 4k + */ + +#define PSP_VERSTAGE_STACK_START 0x49000 +#define PSP_VERSTAGE_STACK_SIZE (4K) + +#endif /* AMD_CEZANNE_PSP_VERSTAGE_ADDR_H */ |