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author | Kangheui Won <khwon@chromium.org> | 2021-04-29 15:19:03 +1000 |
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committer | Martin Roth <martinroth@google.com> | 2021-05-02 18:25:16 +0000 |
commit | b997b0a04e758207a8db9900eb79a3f59c546193 (patch) | |
tree | fa1f65ef91a6f5bfa7f0e46e267feee159317aab /src/soc/amd/cezanne/psp_verstage | |
parent | d8928e438b6bce4af4963eaec8a8e6b29cb32736 (diff) | |
download | coreboot-b997b0a04e758207a8db9900eb79a3f59c546193.tar.xz |
soc/amd/cezanne: add verstage files
Add support for psp_verstage compilation.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Iac48c92a787adabfdaec96b6e8d2e24708d7e652
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/cezanne/psp_verstage')
-rw-r--r-- | src/soc/amd/cezanne/psp_verstage/Makefile.inc | 17 | ||||
-rw-r--r-- | src/soc/amd/cezanne/psp_verstage/stub.c | 31 | ||||
-rw-r--r-- | src/soc/amd/cezanne/psp_verstage/svc.c | 109 | ||||
-rw-r--r-- | src/soc/amd/cezanne/psp_verstage/svc.h | 57 |
4 files changed, 214 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/psp_verstage/Makefile.inc b/src/soc/amd/cezanne/psp_verstage/Makefile.inc new file mode 100644 index 0000000000..8f268ca57d --- /dev/null +++ b/src/soc/amd/cezanne/psp_verstage/Makefile.inc @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only + +verstage-generic-ccopts += -I$(src)/soc/amd/cezanne/psp_verstage/include +verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/cezanne/include + +verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include + +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage + +verstage-y += svc.c +verstage-y += stub.c + +verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S +verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S + +$(obj)/psp_verstage.bin: $(objcbfs)/verstage.elf + $(OBJCOPY_verstage) -O binary $^ $@ diff --git a/src/soc/amd/cezanne/psp_verstage/stub.c b/src/soc/amd/cezanne/psp_verstage/stub.c new file mode 100644 index 0000000000..b3ec7044b4 --- /dev/null +++ b/src/soc/amd/cezanne/psp_verstage/stub.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file contains stub for not-yet-implemented svc in cezanne PSP. + * So this file will and should be removed eventually when psp_verstage works + * correctly in cezanne. + */ + +#include <bl_uapp/bl_syscall_public.h> +#include <console/console.h> +#include <psp_verstage.h> +#include <reset.h> +#include <timer.h> + +uint32_t svc_write_postcode(uint32_t postcode) +{ + return 0; +} + +static uint64_t tmp_timer_value = 0; +void timer_monotonic_get(struct mono_time *mt) +{ + mt->microseconds = tmp_timer_value / 1000; + tmp_timer_value++; +} + +void do_board_reset(void) +{ + printk(BIOS_ERR, "Reset not implemented yet.\n"); + while (1) + ; +} diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c new file mode 100644 index 0000000000..3d10c22663 --- /dev/null +++ b/src/soc/amd/cezanne/psp_verstage/svc.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "svc.h" + +#include <assert.h> +#include <bl_uapp/bl_syscall_public.h> +#include <psp_verstage.h> +#include <stddef.h> + +void svc_exit(uint32_t status) +{ + uint32_t unused = 0; + SVC_CALL0(SVC_EXIT, unused); +} + +void svc_debug_print(const char *string) +{ + uint32_t unused = 0; + SVC_CALL1(SVC_DEBUG_PRINT, (uint32_t)string, unused); +} + +void svc_debug_print_ex(uint32_t dword0, + uint32_t dword1, uint32_t dword2, uint32_t dword3) +{ + uint32_t unused = 0; + SVC_CALL4(SVC_DEBUG_PRINT_EX, dword0, dword1, dword2, dword3, unused); +} + +uint32_t svc_get_boot_mode(uint32_t *boot_mode) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_GET_BOOT_MODE, boot_mode, retval); + return retval; +} + +void svc_delay_in_usec(uint32_t delay) +{ + uint32_t i; + for (i = 0; i < delay * 1000; i++) + asm volatile ("nop"); +} + +uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_GET_SPI_INFO, (uint32_t)spi_rom_info, retval); + return retval; +} + +uint32_t svc_map_fch_dev(enum fch_io_device io_device, + uint32_t arg1, uint32_t arg2, void **io_device_axi_addr) +{ + uint32_t retval = 0; + assert(io_device < FCH_IO_DEVICE_END); + SVC_CALL4(SVC_MAP_FCH_IO_DEVICE, io_device, arg1, arg2, + (uint32_t)io_device_axi_addr, retval); + return retval; +} + +uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, void *io_device_axi_addr) +{ + uint32_t retval = 0; + assert(io_device < FCH_IO_DEVICE_END); + SVC_CALL2(SVC_UNMAP_FCH_IO_DEVICE, (uint32_t)io_device, + (uint32_t)io_device_axi_addr, retval); + return retval; +} + +uint32_t svc_map_spi_rom(void *spi_rom_addr, + uint32_t size, void **spi_rom_axi_addr) +{ + uint32_t retval = 0; + SVC_CALL3(SVC_MAP_SPIROM_DEVICE, spi_rom_addr, size, + (uint32_t)spi_rom_axi_addr, retval); + return retval; +} + +uint32_t svc_unmap_spi_rom(void *spi_rom_addr) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_UNMAP_SPIROM_DEVICE, (uint32_t)spi_rom_addr, retval); + return retval; +} + +uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) +{ + return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset); +} + +uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, + uint32_t *bios_dir_offset) +{ + uint32_t retval = 0; + SVC_CALL2(SVC_UPDATE_PSP_BIOS_DIR, (uint32_t)psp_dir_offset, + (uint32_t)bios_dir_offset, retval); + return retval; +} + +uint32_t save_uapp_data(void *address, uint32_t size) +{ + return svc_save_uapp_data(address, size); +} + +uint32_t svc_save_uapp_data(void *address, uint32_t size) +{ + uint32_t retval = 0; + SVC_CALL2(SVC_COPY_DATA_FROM_UAPP, (uint32_t)address, size, retval); + return retval; +} diff --git a/src/soc/amd/cezanne/psp_verstage/svc.h b/src/soc/amd/cezanne/psp_verstage/svc.h new file mode 100644 index 0000000000..e44948e04b --- /dev/null +++ b/src/soc/amd/cezanne/psp_verstage/svc.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef PSP_VERSTAGE_SVC_H +#define PSP_VERSTAGE_SVC_H + +#define SVC_CALL4(SVC_ID, R0, R1, R2, R3, Ret) \ + __asm__ __volatile__ ( \ + "mov r0, %[reg0]\n\t" \ + "mov r1, %[reg1]\n\t" \ + "mov r2, %[reg2]\n\t" \ + "mov r3, %[reg3]\n\t" \ + "svc %[id]\n\t" \ + "mov %[result], r0\n\t" \ + : [result] "=r" (Ret) /* output */ \ + : [id] "i" (SVC_ID), [reg0] "r" (R0), [reg1] "r" (R1), [reg2] "r" (R2), \ + [reg3] "r" (R3) /* input(s) */ \ + : "r0", "r1", "r2", "r3", "memory", "cc" /* list of clobbered registers */) + +#define SVC_CALL3(SVC_ID, R0, R1, R2, Ret) \ + __asm__ __volatile__ ( \ + "mov r0, %[reg0]\n\t" \ + "mov r1, %[reg1]\n\t" \ + "mov r2, %[reg2]\n\t" \ + "svc %[id]\n\t" \ + "mov %[result], r0\n\t" \ + : [result] "=r" (Ret) /* output */ \ + : [id] "i" (SVC_ID), [reg0] "r" (R0), [reg1] "r" (R1), [reg2] "r" (R2) \ + : "r0", "r1", "r2", "memory", "cc" /* list of clobbered registers */) + +#define SVC_CALL2(SVC_ID, R0, R1, Ret) \ + __asm__ __volatile__ ( \ + "mov r0, %[reg0]\n\t" \ + "mov r1, %[reg1]\n\t" \ + "svc %[id]\n\t" \ + "mov %[result], r0\n\t" \ + : [result] "=r" (Ret) /* output */ \ + : [id] "i" (SVC_ID), [reg0] "r" (R0), [reg1] "r" (R1)/* input(s) */ \ + : "r0", "r1", "memory", "cc" /* list of clobbered registers */) + +#define SVC_CALL1(SVC_ID, R0, Ret) \ + __asm__ __volatile__ ( \ + "mov r0, %[reg0]\n\t" \ + "svc %[id]\n\t" \ + "mov %[result], r0\n\t" \ + : [result] "=r" (Ret) /* output */ \ + : [id] "i" (SVC_ID), [reg0] "r" (R0) /* input(s) */ \ + : "r0", "memory", "cc" /* list of clobbered registers */) + +#define SVC_CALL0(SVC_ID, Ret) \ + __asm__ __volatile__ ( \ + "svc %[id]\n\t" \ + "mov %[result], r0\n\t" \ + : [result] "=r" (Ret) /* output */ \ + : [id] "I" (SVC_ID) /* input(s) */ \ + : "memory", "cc" /* list of clobbered registers */) + +#endif /* PSP_VERSTAGE_SVC_H */ |