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| author | William Wei <wenxu.wei@bitland.corp-partner.google.com> | 2020-06-22 13:30:37 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-29 15:49:04 +0000 |
| commit | 9f6622fb5588a9322b7f1c71bc198d0c2e1dd1bf (patch) | |
| tree | f1df01f559863fe8736d66fe975a0380d90c0a9e /src/soc/amd/common/block/gpio_banks/gpio.c | |
| parent | 3f2f5edfeddb340524166355df563a0632f70013 (diff) | |
| download | coreboot-9f6622fb5588a9322b7f1c71bc198d0c2e1dd1bf.tar.xz | |
soc/intel/tigerlake: Run pmc_set_acpi_mode() during .init in pmc_ops
pmc_set_acpi_mode() should run after Chrome EC dealt with all host event
bits, like SMI mask (otherwise the FAFT firmware_FWScreenCloseLid test
will fail).
BUG=b:153249055
TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage
Change the GBB flag to 0x140 then check SMI mask during depthcharge
phase, make sure it's 0x0000000000000001.
Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com>
Change-Id: Icfff5cc5550f23938343e4d26ef76093bb9cf7c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/common/block/gpio_banks/gpio.c')
0 files changed, 0 insertions, 0 deletions